Device and method for measuring characteristics of a wafer

A device for measuring characteristics of a wafer, comprising:

• a first circuit on the wafer and having a first number of parallelly connected first ring oscillators;
• and
• a second circuit on the wafer and having the first number of parallelly connected second ring oscillators;
• a first driver, coupled to the first circuit, and configured to drive the first circuit using a first clock signal and a second clock signal that are generated from a third clock signal;
• a second driver, coupled to the second circuit, and configured to drive the second circuit using the first clock signal and the second clock signal;
• wherein
• the first clock signal, the second clock signal, and the third clock signal have a first frequency;
• a first duty cycle of the first clock signal is larger than a second duty cycle of the second clock signal;
• each first ring oscillator of the first circuit includes a first portion formed during a front-end-of-line of the wafer and a second portion formed during a back-end-of-line of the wafer,
• each second ring oscillator of the second circuit includes a first portion formed during the front-end-of-line of the wafer and a second portion formed during the back-end-of-line of the wafer,
• the first portion of each first ring oscillator of the first circuit formed during the front-end-of-line of the wafer is electrically disconnected from the second portion of each first ring oscillator of the first circuit formed during the back-end-of-line of the wafer, and
• the first portion of each second ring oscillator of the second circuit formed during the front-end-of-line of the wafer is electrically disconnected from the second portion of each second ring oscillator of the second circuit formed during the back-end-of-line of the wafer.

A device for measuring characteristics of a wafer, comprising:

• a first circuit on the wafer and having a first number of parallelly connected ring oscillators;
• a second circuit on the wafer and having the first number of parallelly connected ring oscillators;
• a first driver, coupled to the first circuit, and configured to drive the first circuit using a first clock signal and a second clock signal;
• a second driver, coupled to the second circuit, and configured to drive the second circuit using the first clock signal and the second clock signal;
• and
• a clock generator configured to generate the first clock signal and the second clock signal using a third clock signal and provide the first clock signal and the second clock signal to the first driver and the second driver, wherein
• the first clock signal, the second clock signal, and the third clock signal have a first frequency;
• a first duty cycle of the first clock signal is larger than a second duty cycle of the second clock signal;
• and
• a rising edge of the first clock signal is not aligned with a rising edge of the second clock signal, a falling edge of the first clock signal is not aligned with a falling edge of the second clock signal, each ring oscillator of the second circuit includes a first portion formed during a front-end-of-line of the wafer and a second portion formed during a back-end-of-line of the wafer, and the first portion of each ring oscillator of the second circuit formed during the front-end-of-line of the wafer is electrically disconnected from the second portion of each oscillator of the second circuit formed during the back-end-of-line of the wafer.