# US 12,114,514 B2 · Method for manufacturing memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,114,514 B2
- Document ID: US12114514B2
- Status: Granted
- Kind: B2
- Application number: 18/519,230
- Filed: 2023-11-27
- Published: 2024-03-14
- Granted: 2024-10-08
- Earliest claimed: 2021-08-03
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Feng-Min Lee; Erh-Kun Lai; Dai-Ying Lee; Yu-Hsuan Lin; Po-Hao Tseng; Ming-Hsiu Lee
- Web page: https://patentgrep.com/patent/US12114514B2

## CPC

- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10N 50/01: Manufacture or treatment
- H10N 70/066: {by filling of openings, e.g. damascene method}
- G11C 11/1659: {Cell access}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- G11C 13/003: {Cell access}
- G11C 2213/71: Three dimensional array
- G11C 2213/79: Array wherein the access device being a transistor
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

## Claims

### Claim 1

A method for manufacturing a memory device, comprising:
providing a stacked structure disposed on a substrate, the stacked structure comprising a plurality of sacrificial layers and a plurality of insulating layers alternately stacked along a first direction;
forming a plurality of openings passing through the stacked structure;
removing portions of the sacrificial layers to form a plurality of grooves between the sacrificial layers, the insulating layers and the openings;
forming a channel material layer in the grooves, wherein the channel material layer includes a first side and a second side, and the first side and the second side are opposite to each other;
forming a vertical hole extending along the first direction on the first side of the channel material layer;
filling a conductive material in the vertical hole to form a first conductive pillar;
forming an extension hole extending along the first direction on the second side of the channel material layer, and the channel material layer becomes a channel layer;
sequentially filling a memory material and a conductive material in the extension hole to form a memory structure and a second conductive pillar, respectively, wherein the memory structure surrounds the second conductive pillar and comprises a resistive memory material; and
removing the sacrificial layers and filling a conductive material at positions where the sacrificial layers are removed, to form a plurality of conductive layers.

### Claim 2 (depends on 1)

The method for manufacturing the memory device according to claim 1, wherein the memory structure is disposed between the first conductive pillar and the channel layer.

### Claim 3 (depends on 1)

The method for manufacturing the memory device according to claim 1, wherein the memory structure has an inner surface and an outer surface, the inner surface is opposite to the outer surface, the inner surface directly contacts the second conductive pillar, and the outer surface directly contacts the channel layer, so that the second conductive pillar and the channel layer are separated by the memory structure.

### Claim 4 (depends on 1)

The method for manufacturing the memory device according to claim 1, wherein the substrate has an upper surface, the insulating layers and the conductive layers form a stack, and the stack is formed on the upper surface, the conductive layers and the insulating layers respectively extend along a second direction, and the second direction is intersected with the first direction, and a length of the conductive layers in the second direction is smaller than a length of the insulating layers in the second direction.

### Claim 5 (depends on 1)

The method for manufacturing the memory device according to claim 1, wherein the channel layer comprises a plurality of channel portions, the channel portions correspond to the conductive layers of different layers, and the channel portions are separated from each other.

### Claim 6 (depends on 1)

The method for manufacturing the memory device according to claim 1, further comprising forming a plurality of oxide material layers in the grooves before forming the channel material layer.

### Claim 7 (depends on 1)

The method for manufacturing the memory device according to claim 1, wherein the first conductive pillar, the second conductive pillar, the channel layer, and the memory structure correspond to a first memory string.

### Claim 8 (depends on 7)

The method for manufacturing the memory device according to claim 7, further comprising forming a second memory string, the second memory string being neighboring to the first memory string, and the first memory string and the second memory string sharing the first conductive pillar.

### Claim 9 (depends on 7)

The method for manufacturing the memory device according to claim 7, further comprising forming a second memory string, the second memory string being neighboring to the first memory string and separated from the first memory string.

### Claim 10 (depends on 1)

The method for manufacturing the memory device according to claim 1, wherein the resistive memory material is a transition metal oxide, a conductive bridge memory material, a phase change memory material, or a magnetoresistive memory material.