# US 12,114,513 B2 · Memory device and manufacturing method thereof

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- Number: US 12,114,513 B2
- Document ID: US12114513B2
- Status: Granted
- Kind: B2
- Application number: 17/876,575
- Filed: 2022-07-29
- Published: 2022-12-08
- Granted: 2024-10-08
- Earliest claimed: 2020-07-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chao-I Wu; Yu-Ming Lin
- Web page: https://patentgrep.com/patent/US12114513B2

## CPC

- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10B 53/30: characterised by the memory core region
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/881: {Switching materials}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory device and a manufacturing method thereof are provided. The memory device includes word lines, channel layer, gate dielectric layers, a conductive pillar and a storage pillar. The word lines extend along a first direction over a substrate, and are vertically spaced apart from one another. The channel layers respectively line along a sidewall of one of the word lines. The gate dielectric layers respectively line between one of the word lines and one of the channel layers. The conductive pillar and the storage pillar penetrate through the channel layers. The storage pillar includes an inner electrode, a switching layer and an outer electrode. The switching layer wraps around the inner electrode. The outer electrode laterally surrounds the switching layer, and includes annulus portions vertically spaced apart from one another and each in lateral contact with a corresponding one of the channel layers.

## Claims

### Claim 1

A memory device, comprising:
a storage pillar, standing on a substrate and comprising:
an inner electrode;
a switching layer, wrapping around the inner electrode, and
outer electrodes, laterally enclosing the switching layer, and vertically separated from one another; and
access transistors, stacked on the substrate and respectively coupled to one of the outer electrodes of the storage pillar, wherein the storage pillar penetrates through channel layers of the access transistors.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein the memory device is elevated from a semiconductor substrate in a semiconductor device.

### Claim 3 (depends on 2)

The memory device according to claim 2, wherein the memory device is embedded in a back-end-of-line (BEOL) structure of the semiconductor device.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein the access transistors further comprise:
gate dielectric layers, respectively extending along a sidewall of one of the channel layers;
word lines, respectively in lateral contact with one of the channel layers through one of the gate dielectric layers; and
a conductive pillar, penetrating through the channel layers and laterally spaced apart from the storage pillar.

### Claim 5 (depends on 4)

The memory device according to claim 4, wherein the storage pillar and the conductive pillar are laterally spaced apart from the word lines through the gate dielectric layers.

### Claim 6 (depends on 4)

The memory device according to claim 4, wherein composite layers each comprising one of the channel layers, one of the gate dielectric layers and one of the word lines are vertically separated from one another.

### Claim 7 (depends on 6)

The memory device according to claim 6, wherein the channel layer, the gate dielectric layer and the word line in each of the composite layers are formed with substantially identical thickness.

### Claim 8 (depends on 6)

The memory device according to claim 6, further comprising isolation layers and spacer layers, wherein adjacent ones of the composite layers are vertically separated from each other through one of the isolation layers and one of the spacer layers.

### Claim 9 (depends on 8)

The memory device according to claim 8, wherein the storage pillar and the conductive pillar penetrate through the isolation layers and the spacer layers.

### Claim 10 (depends on 8)

The memory device according to claim 8, wherein the isolation layers are formed of a first insulating material, and the spacer layers are formed of a second insulating material different from the first insulating material.

### Claim 11

A memory device, comprising:
a storage pillar, standing on a substrate, and comprising:
an inner electrode, formed as a pillar structure;
outer electrodes, laterally enclosing the switching layer, and vertically separated from one another;
a switching layer, separating the inner electrode pillar from the outer electrodes, and having lateral protruding portions extending in between the outer electrodes; and
access transistors, stacked on the substrate and respectively coupled to one of the outer electrodes of the storage pillar, wherein the outer electrodes of the storage pillar are respectively functioned as a source/drain terminal of one of the access transistors.

### Claim 12 (depends on 11)

The memory device according to claim 11, wherein the access transistors comprise:
composite layers, vertically separated from one another, and each comprising a channel layer, a word line and a gate dielectric layer extending between the channel layer and the word line, wherein the storage pillar penetrates through the composite layers; and
a conductive pillar, extending through the composite layers and functioned as a common source/drain terminal of the access transistors.

### Claim 13 (depends on 12)

The memory device according to claim 12, further comprising isolation layers and spacer layers, wherein adjacent ones of the composite layers are separated from each other via one of the isolation layers and one of the spacer layers.

### Claim 14 (depends on 13)

The memory device according to claim 13, wherein the outer electrodes are in lateral contact with the composite layers and the isolation layers, and the lateral protruding portions of the switching layer are in lateral contact with the spacer layers.

### Claim 15 (depends on 13)

The memory device according to claim 13, further comprising:
annulus spacers, separating the spacer layers from the conductive pillar.

### Claim 16 (depends on 15)

The memory device according to claim 15, wherein the annulus spacers each laterally surround a narrow portion of the conductive pillar, and located between adjacent thick portions of the conductive pillar.

### Claim 17

A memory device, comprising:
a storage pillar, standing on a substrate, and comprising:
an inner electrode;
outer electrodes, laterally enclosing the switching layer, and vertically separated from one another; and
a switching layer, separating the inner electrode pillar from the outer electrodes;
access transistors, respectively coupled to one of the outer electrodes, and comprising a conductive pillar standing on the substrate and composite layers separately stacked on the substrate and penetrated through by the storage pillar as well as the conductive pillar, wherein the composite layers respectively comprise a channel layer, a gate dielectric layer and a word line in lateral contact with the channel layer through the gate dielectric layer; and
spacer layers, stacked on the substrate, wherein adjacent ones of the composite layers are separated from each other through one of the spacer layers, and the spacer layers each have a lateral protruding portion protruding into the storage pillar and separating adjacent ones of the outer electrodes.

### Claim 18 (depends on 17)

The memory device according to claim 17, wherein the protruding portions of the spacer layers laterally protrude into the storage pillar with respect to the composite layers.

### Claim 19 (depends on 17)

The memory device according to claim 17, further comprising:
isolation layers, stacked on the substrate, wherein adjacent ones of the composite layers are separated from each other through one of the isolation layers and one of the composite layers, and the protruding portions of the spacer layers laterally protrude into the storage pillar with respect to the composite layers and the isolation layers.

### Claim 20 (depends on 19)

The memory device according to claim 19, wherein the isolation layers and the spacer layers are in direct contact with the conductive pillar.