# US 12,114,511 B2 · Semiconductor device, integrated circuit and method of manufacturing the same

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- Number: US 12,114,511 B2
- Document ID: US12114511B2
- Status: Granted
- Kind: B2
- Application number: 17/462,577
- Filed: 2021-08-31
- Published: 2023-03-02
- Granted: 2024-10-08
- Earliest claimed: 2021-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Hui-Hsien Wei; Yen-Chung Ho; Chia-Jung Yu; Yong-Jie Wu; Pin-Cheng Hsu
- Web page: https://patentgrep.com/patent/US12114511B2

## CPC

- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; a gate dielectric layer disposed over the gate electrode; source/drain electrodes disposed above the gate electrode; and an active layer disposed above the gate electrode. A protection layer is disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a thin-film transistor (TFT) disposed over the substrate, the TFT comprising:
a gate electrode;
a gate dielectric layer disposed over the gate electrode;
source/drain electrodes disposed above the gate electrode; and
an active layer disposed above the gate electrode;
a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT; and
a protection layer disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT, wherein the protection layer includes oxide semiconductor material.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a portion of the protection layer is disposed between the source/drain electrodes and the MRAM cell, and the oxide semiconductor material includes IGZO, ITZO, IZO, AGZO, or a combination thereof.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein another portion of the protection layer is disposed between the active layer and the gate dielectric layer.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the protection layer extends from the source electrode to the drain electrode.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a portion of the protection layer is disposed in an opening defined by the source/drain electrodes.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein another portion of the protection layer electrically connects the MRAM cell to the source/drain electrodes.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the protection layer has a projection area overlapping at least a portion of the active layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the protection layer has a projection area overlapping at least a portion of the source/drain electrodes.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the protection layer has a projection area overlapping at least a portion of the gate electrode and at least a portion of the source/drain electrodes.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the protection layer is disposed on the source/drain electrodes and has a shape in conformity with the shape of the source/drain electrodes and an opening defined by the source/drain electrodes.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the active layer has an upper surface higher than an upper surface of the source/drain electrodes.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the TFT is disposed in an inter-metal dielectric (IMD) layer and an upper surface of the gate electrode is in substantially coplanar with a bottom surface of the gate dielectric layer.

### Claim 13

An integrated circuit, comprising:
a logic region disposed on a substrate; and
an embedded memory region disposed over the substrate, comprising:
a thin-film transistor (TFT) disposed over the substrate, the TFT comprising:
a gate electrode;
a gate dielectric layer disposed over the gate electrode;
source/drain electrodes disposed above the gate dielectric layer and contacting the gate dielectric layer; and
an active layer disposed above the gate electrode;
a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT; and
a protection layer disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT, wherein the protection layer is conformal to the gate dielectric layer and the source/drain electrodes.

### Claim 14 (depends on 13)

The integrated circuit of claim 13, wherein a portion of the protection layer is disposed between the source/drain electrodes and the MRAM cell and another portion of the protection layer is disposed between the active layer and the gate dielectric layer.

### Claim 15 (depends on 13)

The integrated circuit of claim 13, wherein the protection layer has a projection area overlapping at least a portion of the gate electrode, at least a portion of the active layer, and at least a portion of the source/drain electrodes.

### Claim 16 (depends on 13)

The integrated circuit of claim 13, wherein the protection layer is disposed on the source/drain electrodes and has a shape in conformity with the shape of the source/drain electrodes and an opening defined by the source/drain electrodes.

### Claim 17 (depends on 13)

The integrated circuit of claim 13, wherein the active layer has an upper surface higher than an upper surface of the source/drain electrodes.

### Claim 18 (depends on 13)

The integrated circuit of claim 13, wherein the logic region comprises a transistor and the TFT is spaced from the transistor by at least two dielectric layers.

### Claim 19

A method of manufacturing a semiconductor device, comprising:
disposing a transistor on a substrate;
disposing an inter-layer dielectric (ILD) layer over the transistor;
disposing an IMD layer over the ILD layer;
disposing a TFT over the IMD layer; and
disposing a protection layer over the TFT, wherein the protection layer includes oxide semiconductor material.

### Claim 20 (depends on 19)

The method of claim 19, wherein the protection layer is disposed between an active layer and a gate dielectric layer of the TFT and has a projection area overlapping at least a portion of a gate electrode and source/drain electrodes of the TFT.