# US 12,114,508 B2 · Semiconductor device and method for fabricating the same

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- Number: US 12,114,508 B2
- Document ID: US12114508B2
- Status: Granted
- Kind: B2
- Application number: 17/548,607
- Filed: 2021-12-13
- Published: 2023-05-18
- Granted: 2024-10-08
- Earliest claimed: 2021-11-12
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Po-Kuang Hsieh; Shih-Hung Tsai; Chun-Hsien Lin
- Web page: https://patentgrep.com/patent/US12114508B2

## CPC

- H10B 53/30: characterised by the memory core region
- H10D 1/682: {having dielectrics comprising perovskite structures}
- H10D 1/692: {Electrodes}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
forming a first inter-metal dielectric (IMD) layer on a substrate;
forming a first trench and a second trench in the first IMD layer, wherein bottom surfaces of the first trench and the second trench expose the first IMD layer;
forming a bottom electrode in the first trench and the second trench;
forming a ferroelectric (FE) layer on the bottom electrode; and
forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
patterning the top electrode and the FE layer;
forming a hard mask on the FeRAM;
forming a second IMD layer on the hard mask; and
forming a first metal interconnection and a second metal interconnection in the second IMD layer.

### Claim 3 (depends on 2)

The method of claim 2, further comprising forming the hard mask on the bottom electrode and the top electrode.

### Claim 4 (depends on 2)

The method of claim 2, wherein the first metal interconnection connects the top electrode.

### Claim 5 (depends on 2)

The method of claim 2, wherein the second metal interconnection connects the bottom electrode.

### Claim 6 (depends on 1)

The method of claim 1, wherein a sidewall of the top electrode is aligned with a sidewall of the FE layer.

### Claim 7

A semiconductor device, comprising:
an inter-metal dielectric (IMD) layer on a substrate; and
a ferroelectric random access memory (FeRAM) on the ILD layer, wherein the FeRAM comprises:
a first trench and a second trench in the IMD layer, wherein bottom surfaces of the first trench and the second trench expose the first IMD layer;
a bottom electrode in the first trench and the second trench;
a ferroelectric (FE) layer on the bottom electrode; and
a top electrode on the FE layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising:
a hard mask on the FeRAM;
a second IMD layer on the hard mask; and
a first metal interconnection and a second metal interconnection in the second IMD layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the hard mask is on the bottom electrode and the top electrode.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the first metal interconnection connects the top electrode.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the second metal interconnection connects the bottom electrode.

### Claim 12 (depends on 7)

The semiconductor device of claim 7, wherein a sidewall of the top electrode is aligned with a sidewall of the FE layer.