# US 12,114,507 B2 · Capping layer over FET FeRAM to increase charge mobility

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,114,507 B2
- Document ID: US12114507B2
- Status: Granted
- Kind: B2
- Application number: 18/335,167
- Filed: 2023-06-15
- Published: 2023-10-12
- Granted: 2024-10-08
- Earliest claimed: 2021-02-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Rainer Yen-Chieh Huang; Hai-Ching Chen; Chung-Te Lin
- Web page: https://patentgrep.com/patent/US12114507B2

## CPC

- H10B 51/30: characterised by the memory core region
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6746: {Amorphous silicon}
- H10D 30/6748: {having a multilayer structure or superlattice structure}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/689: {having ferroelectric layers}
- H10W 20/42: Vias, e.g. via plugs
- H10B 51/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.

## Claims

### Claim 1

An integrated chip, comprising:
a gate electrode arranged over a substrate;
a gate dielectric layer arranged over the gate electrode and comprising a ferroelectric material;
an active structure arranged over the gate dielectric layer and comprising a semiconductor material;
a source contact and a drain contact arranged over the active structure; and
a capping structure arranged over the active structure and between the source contact and the drain contact, wherein the capping structure comprises a first layer comprising a first metal material and a second layer arranged over the first layer and comprising a second metal material.

### Claim 2 (depends on 1)

The integrated chip according to claim 1, wherein the active structure comprises a diffusion region directly under the capping structure, and wherein the diffusion region comprises oxide of the first metal material.

### Claim 3 (depends on 1)

The integrated chip according to claim 1, wherein the capping structure has a higher affinity for oxygen than the active structure.

### Claim 4 (depends on 1)

The integrated chip according to claim 1, wherein the active structure comprises a plurality of cocktails layers and a plurality of first active layers alternatingly stacked, wherein the plurality of cocktail layers individually have multiple different metal oxides that are intermixed, and wherein the plurality of first active layers individually have a single metal oxide different than the multiple different metal oxides.

### Claim 5 (depends on 4)

The integrated chip according to claim 4, wherein the active structure further comprises a second active layer overlying the plurality of cocktails layers and the plurality of first active layers, and wherein the second active layer has only one of the multiple different metal oxides.

### Claim 6 (depends on 1)

The integrated chip according to claim 1, wherein a top surface of the active structure comprises a metal oxide, and wherein the metal oxide has a more negative bonding energy than another metal oxide of the active structure.

### Claim 7 (depends on 6)

The integrated chip according to claim 6, wherein the source contact directly contacts the top surface of the active structure.

### Claim 8

An integrated chip, comprising:
a gate electrode arranged over a substrate;
a gate dielectric layer arranged over the gate electrode and comprising a ferroelectric material;
an active structure arranged over the gate dielectric layer and comprising a semiconductor material;
a source contact and a drain contact arranged over the active structure; and
a capping structure arranged over the active structure and between the source contact and the drain contact;
wherein the active structure comprises a plurality of metal oxides, which includes a first metal oxide having a highest bond energy amongst the plurality of metal oxides, and further comprises a layer of the first metal oxide separating a remainder of the active structure from the capping structure.

### Claim 9 (depends on 8)

The integrated chip according to claim 8, wherein the capping structure comprises a metal alloy with multiple metal elements.

### Claim 10 (depends on 8)

The integrated chip according to claim 8, wherein the plurality of metal oxides comprise a second metal oxide, wherein the active structure further comprise a plurality of cocktail layers between the gate dielectric layer and the layer of the first metal oxide, and wherein the plurality of cocktail layers individually comprise a mixture of the first metal oxide and the second metal oxide in which regions of the second metal oxide are buried in a region of the first metal oxide.

### Claim 11 (depends on 10)

The integrated chip according to claim 10, wherein the plurality of metal oxides comprise a third metal oxide, wherein the active structure further comprises a plurality of layers of the third metal oxide alternatingly stacked with the plurality of cocktail layers, and wherein the third metal oxide has higher crystallinity than the first and second metal oxides.

### Claim 12 (depends on 8)

The integrated chip according to claim 8, wherein the capping structure directly contacts the layer of the first metal oxide.

### Claim 13 (depends on 8)

The integrated chip according to claim 8, wherein a topmost surface of the capping structure is level with a topmost surface of the source contact and a topmost surface of the drain contact.

### Claim 14 (depends on 8)

The integrated chip according to claim 8, wherein a bottommost surface of the source contact is level with a bottommost surface of the capping structure.

### Claim 15

An integrated chip, comprising:
a gate electrode over a substrate;
a gate dielectric layer over the gate electrode;
a multilayer stack over the gate dielectric layer and comprising a plurality of zinc oxide layers and a plurality of cocktails layers, wherein the cocktails layers are alternatingly stacked with the zinc oxide layers and individually comprise a mixture of gallium oxide and indium oxide;
a source contact and a drain contact over the multilayer stack; and
a capping structure over the multilayer stack and between the source contact and the drain contact, wherein the capping structure comprises aluminum and calcium.

### Claim 16 (depends on 15)

The integrated chip according to claim 15, further comprising:
a gallium oxide layer separating the multilayer stack from the capping structure.

### Claim 17 (depends on 16)

The integrated chip according to claim 16, wherein the gallium oxide layer directly contacts the source contact and the drain contact and further directly contacts the multilayer stack at one of the zinc oxide layers.

### Claim 18 (depends on 15)

The integrated chip according to claim 15, wherein the plurality of cocktails layers are amorphous.

### Claim 19 (depends on 15)

The integrated chip according to claim 15, wherein the capping structure comprises a layer of calcium and a layer of aluminum that are vertically stacked.

### Claim 20 (depends on 15)

The integrated chip according to claim 15, wherein the gate electrode, the gate dielectric layer, and the multilayer stack share a common width.