# US 12,114,499 B2 · Block-on-block memory array architecture using bi-directional staircases > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,114,499 B2 - Document ID: US12114499B2 - Status: Granted - Kind: B2 - Application number: 17/720,223 - Filed: 2022-04-13 - Published: 2022-07-28 - Granted: 2024-10-08 - Earliest claimed: 2019-12-17 - Assignees: Lodestar Licensing Group LLC - Applicants: Micron Technology, Inc. - Inventors: Aaron S. Yip - Web page: https://patentgrep.com/patent/US12114499B2 ## CPC - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 11/5621: {using charge storage in a floating gate} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10P 50/264: {by chemical means} - H10W 20/067: {by modifying the pattern of conductive parts} - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions. ## Claims ### Claim 1 A device, comprising: a memory array having bi-directional staircases and a distributed stadium structure including a plurality of stadiums, wherein each respective stadium among the stadiums includes dummy treads, and wherein a shape of at least a portion of the respective stadium is defined by ends of the dummy treads; wherein the bi-directional staircases includes: a first staircase descending in a first direction; and a second staircase descending in a second direction opposite the first direction; and wherein the device further comprises a plurality of conductive connectors connected between the first staircase and the second staircase, each respective connector among the plurality of conductive connectors configured to connect a first layer in the first staircase to a second layer in the second staircase. ### Claim 2 (depends on 1) The device of claim 1, wherein the dummy treads are inactive remnants that remain after formation of the distributed stadium structure. ### Claim 3 (depends on 2) The device of claim 2, wherein the distributed stadium structure is formed using at least one chop etch. ### Claim 4 (depends on 1) The device of claim 1, wherein each staircase comprises word-line tiers. ### Claim 5 (depends on 4) The device of claim 4, wherein each staircase has contacts configured to vertically contact landing pads on the word-line tiers. ### Claim 6 (depends on 4) The device of claim 4, wherein each stadium has a shape partially defined by ends of the word-line tiers. ### Claim 7 (depends on 1) The device of claim 1, wherein the stadiums descend in depth. ### Claim 8 (depends on 1) The device of claim 1, wherein the second staircase is adjacent to the first staircase. ### Claim 9 A device, comprising: a memory array having bi-directional staircases, wherein: the device has a distributed stadium structure including a plurality of stadiums; each respective staircase among the bi-directional staircases comprises word-line tiers; and each stadium among the stadiums has a shape partially defined by ends of the word-line tiers; wherein the stadiums descend in depth when moving down the respective staircase; wherein the distributed stadium structure has a first staircase descending in a first direction and a second staircase descending in a second direction opposite the first direction; and wherein the device further comprises a plurality of conductive connectors connected between the first staircase and the second staircase, each respective connector among the plurality of conductive connectors configured to connect a first word-line tie in the first staircase to a second word-line tie in the second staircase. ### Claim 10 (depends on 9) The device of claim 9, wherein the conductive connectors electrically connect opposite portions of corresponding word-lines in a block of the memory array. ### Claim 11 (depends on 9) The device of claim 9, wherein the conductive connectors include a conductive plug or a conductive vertical interconnect. ### Claim 12 A device, comprising: a plurality of tiers formed by a stack of conductive layers separated by insulating layers, wherein the tiers are for accessing data stored in a memory array; a first staircase having steps that descend in a first direction, with each step in the first staircase formed by one of the conductive layers; a second staircase having steps that descend in a second direction opposite to the first direction, with each step in the second staircase formed by one of the conductive layers; and a plurality of conductive connectors connected between the first staircase and the second staircase, each respective connector among the plurality of conductive connectors configured to connect a first conductive layer in the first staircase to a second conductive layer in the second staircase. ### Claim 13 (depends on 12) The device of claim 12, wherein the respective connector include a conductive plug or a conductive vertical interconnect.