# US 12,114,496 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 12,114,496 B2
- Document ID: US12114496B2
- Status: Granted
- Kind: B2
- Application number: 18/225,561
- Filed: 2023-07-24
- Published: 2023-11-16
- Granted: 2024-10-08
- Earliest claimed: 2020-05-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Meng-Han Lin; Te-An Chen
- Web page: https://patentgrep.com/patent/US12114496B2

## CPC

- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/49: comprising different types of peripheral transistor
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

## Claims

### Claim 1

A semiconductor device including:
a first circuit formed in a first circuit area of a substrate;
a second circuit formed in a second circuit area of the substrate; and
an isolation insulating layer disposed between the first circuit area and the second circuit area, wherein:
an upper surface of the isolation insulating layer comprises four horizontal surfaces that include a top surface, a first middle surface lower than the top surface, a second middle surface lower than the first middle surface and a bottom surface lower than the second middle surface, and
the top surface, the first middle surface, the second middle surface and the bottom surface are arranged in this order from the first circuit.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second circuit includes a memory device.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a horizontal length of the bottom surface is longer than horizontal lengths of the first middle surface and the second middle surface.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the upper surface of the isolation insulating layer further comprises a first slope connecting the second middle surface and the bottom surface.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a height difference between the second middle surface and the bottom surface is greater than a height difference between the first middle surface and the second middle surface.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the height difference between the second middle surface and the bottom surface is greater than a height difference between the top surface and the first middle surface.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein:
the isolation insulating layer is at least partially embedded in the substrate, and
a topology of a bottom surface of the isolation insulating layer in contact with the substrate is different from a topology of the upper surface of the isolation insulating layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the bottom surface of the isolation insulating layer in contact with the substrate has two horizontal portions connected by a slope.

### Claim 9

A semiconductor device including:
a non-volatile memory cell formed in a memory cell area of a substrate;
a first circuit formed in a first circuit area of the substrate; and
an isolation insulating layer disposed between the memory cell area and the first circuit area, wherein:
an upper surface of the isolation insulating layer comprises a top horizontal surface and a middle horizontal surface lower than the top horizontal surface, and
the top horizontal surface and the middle horizontal surface are connected by a first slope, a first step and a second slope.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the upper surface further comprises a bottom horizontal surface lower than the middle horizontal surface.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the middle horizontal surface and the bottom horizontal surface are connected by a second step.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein a vertical height of the second step is in a range from 1 nm to 50 nm.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein a horizontal length of the bottom horizontal surface is longer than a horizontal length of the middle horizontal surface.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein a vertical height of the first slope is in a range from 1 nm to 50 nm and a horizontal width of the first slope is in a range from 1 nm to 50 nm.

### Claim 15 (depends on 9)

The semiconductor device of claim 9, wherein a vertical height of the first step is in a range from 1 nm to 50 nm.

### Claim 16 (depends on 9)

The semiconductor device of claim 9, wherein a vertical height of the second step is in a range from 1 nm to 50 nm and a horizontal width of the second slope is in a range from 1 nm to 50 nm.

### Claim 17

A method of manufacturing a semiconductor device, the method comprising:
forming a trench in a substrate at a transition area between a first circuit area and a second circuit area;
forming an isolation insulating layer by filling the trench with an insulating material, the isolation insulating layer including an upper surface having a slope disposed between a top portion and a bottom portion;
forming one or more steps on the upper surface of the isolation insulating layer between the top portion and the bottom portion; and
forming one or more dielectric layers and a polysilicon layer over an entirety of an upper surface of the isolation insulating layer.

### Claim 18 (depends on 17)

The method of claim 17, further comprising performing a first patterning operation on the polysilicon layer and at least one of the one or more dielectric layers.

### Claim 19 (depends on 18)

The method of claim 18, wherein the one or more dielectric layers includes a bottom layer, a middle layer and a top layer, and
the middle layer and the bottom layer are not patterned over the isolation insulating layer in the first patterning operation.

### Claim 20 (depends on 19)

The method of claim 19, further comprising performing a second patterning operation on the middle layer and the bottom layer.