# US 12,114,494 B2 · 3D memory semiconductor device and structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,114,494 B2 - Document ID: US12114494B2 - Status: Granted - Kind: B2 - Application number: 17/461,075 - Filed: 2021-08-30 - Published: 2022-01-06 - Granted: 2024-10-08 - Earliest claimed: 2017-02-04 - Assignees: Monolithic 3D Inc. - Applicants: Monolithic 3D Inc. - Inventors: Zvi Or-Bach; Jin-Woo Han; Eli Lusky - Web page: https://patentgrep.com/patent/US12114494B2 ## CPC - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/0475: {comprising two or more independent storage sites which store independent data} - G11C 16/10: Programming or data input circuits - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 17/165: {Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002)} - H10D 64/037: {comprising charge-trapping insulators} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A 3D memory device, the device including: a first vertical pillar, the first vertical pillar includes a transistor source; a second vertical pillar, the second vertical pillar includes the transistor drain, where the first vertical pillar and the second vertical pillar each functions as a source or functions as a drain for a plurality of overlaying horizontally-oriented memory transistors, where at least of one of the plurality of overlaying horizontally-oriented memory transistors is disposed between the first vertical pillar and the second vertical pillar, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following a same lithography step, and where the first vertical pillar includes metal. ## Claims ### Claim 1 A 3D memory device, the device comprising: a first vertical pillar, said first vertical pillar comprises a transistor source; and a second vertical pillar, said second vertical pillar comprises a transistor drain, wherein said first vertical pillar and said second vertical pillar each comprises a source or a drain for a first plurality of self-aligned overlaying horizontally-oriented memory transistors, wherein at least of one of said first plurality of self-aligned overlaying horizontally-oriented memory transistors is disposed between said first vertical pillar and said second vertical pillar, wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned gate, wherein each self-aligned gate is disposed atop of a self-aligned underlying gate, wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a self-aligned channel region, and wherein at least two of the self-aligned channel region of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprise direct connection. ### Claim 2 (depends on 1) The 3D memory device according to claim 1, wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a tunneling oxide region and a self-aligned charge trap region, and wherein said tunneling oxide region is thinner than 1 nm or does not exist, which enables said 3D memory device to operate at high speed. ### Claim 3 (depends on 1) The 3D memory device according to claim 1, further comprising: a plurality of self-aligned memory control circuits; wherein said plurality of self-aligned memory control circuits provide a periodic memory refresh operation to said first plurality of self-aligned overlaying horizontally-oriented memory transistors. ### Claim 4 (depends on 1) The 3D memory device according to claim 1, wherein said first vertical pillar comprises metal and does not comprise n+ type doped silicon. ### Claim 5 (depends on 1) The 3D memory device according to claim 1, further comprising: a third vertical pillar; wherein said third vertical pillar and said second vertical pillar each comprise a source or comprise a drain for a second plurality of self-aligned overlaying horizontally-oriented memory transistors. ### Claim 6 (depends on 1) The 3D memory device according to claim 1, wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned charge trap region. ### Claim 7 A 3D memory device, the device comprising: a first vertical pillar, said first vertical pillar comprises a transistor source; and a second vertical pillar, said second vertical pillar comprises a transistor drain, wherein said first vertical pillar and said second vertical pillar each comprises a source or a drain for a first plurality of self-aligned overlaying horizontally-oriented memory transistors, wherein at least of one of said first plurality of self-aligned overlaying horizontally-oriented memory transistors is disposed between said first vertical pillar and said second vertical pillar, wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned gate, wherein each self-aligned gate is disposed atop of a self-aligned underlying gate, wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a self-aligned channel region, wherein at least two of the self-aligned channel region of said first plurality of self-aligned horizontally-oriented memory transistors comprise direct connection, wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a tunneling oxide region and a self-aligned charge trap region, and wherein said tunneling oxide region is thinner than 1 nm or does not exist, which enables said 3D memory device to operate at high speed. ### Claim 8 (depends on 7) The 3D memory device according to claim 7, further comprising: a plurality of self-aligned memory control circuits; wherein said plurality of self-aligned memory control circuits provide a periodic memory refresh operation to said first plurality of self-aligned overlaying horizontally-oriented memory transistors. ### Claim 9 (depends on 7) The 3D memory device according to claim 7, wherein said first vertical pillar comprises metal and does not comprise n+ type doped silicon. ### Claim 10 (depends on 7) The 3D memory device according to claim 7, further comprising: a third vertical pillar; wherein said third vertical pillar and said second vertical pillar each comprise a source or comprise a drain for a second plurality of self-aligned overlaying horizontally-oriented memory transistors. ### Claim 11 (depends on 7) The 3D memory device according to claim 7, wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned charge trap region. ### Claim 12 (depends on 7) The 3D memory device according to claim 7, wherein said first vertical pillar and said second vertical pillar each comprise a filled cylindrical shape. ### Claim 13 (depends on 7) The 3D memory device according to claim 7, wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a unique channel region, and wherein each of said unique channel regions is isolated from each other. ### Claim 14 A 3D memory device, the device comprising: a first vertical pillar, said first vertical pillar comprises a transistor source; and a second vertical pillar, said second vertical pillar comprises a transistor drain, wherein said first vertical pillar and said second vertical pillar each comprises a source or a drain for a first plurality of self-aligned overlaying horizontally-oriented memory transistors, wherein at least of one of said first plurality of self-aligned overlaying horizontally-oriented memory transistors is disposed between said first vertical pillar and said second vertical pillar, wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned gate, wherein each self-aligned gate is disposed atop of a self-aligned underlying gate, wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a self-aligned channel region, wherein at least two of the self-aligned channel region of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprise direct connection, and wherein said first vertical pillar comprises metal and does not comprise n+ type doped silicon. ### Claim 15 (depends on 14) The 3D memory device according to claim 14, wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a tunneling oxide region and a self-aligned charge trap region, and wherein said tunneling oxide region is thinner than 1 nm or does not exist, which enables said 3D memory device to operate at high speed. ### Claim 16 (depends on 14) The 3D memory device according to claim 14, further comprising: a plurality of self-aligned memory control circuits; wherein said plurality of self-aligned memory control circuits provide a periodic memory refresh operation to said first plurality of self-aligned overlaying horizontally-oriented memory transistors. ### Claim 17 (depends on 14) The 3D memory device according to claim 14, further comprising: a third vertical pillar; wherein said third vertical pillar and said second vertical pillar each comprise a source or comprise a drain for a second plurality of self-aligned overlaying horizontally-oriented memory transistors. ### Claim 18 (depends on 14) The 3D memory device according to claim 14, wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned charge trap region. ### Claim 19 (depends on 14) The 3D memory device according to claim 14, wherein said first vertical pillar and said second vertical pillar each comprise a filled cylindrical shape. ### Claim 20 (depends on 14) The 3D memory device according to claim 14, wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a unique channel region, and wherein each of said unique channel regions is isolated from each other.