# US 12,114,490 B2 · Semiconductor device and method of forming the same

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- Number: US 12,114,490 B2
- Document ID: US12114490B2
- Status: Granted
- Kind: B2
- Application number: 17/558,323
- Filed: 2021-12-21
- Published: 2023-06-22
- Granted: 2024-10-08
- Earliest claimed: 2021-12-21
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Naoyoshi Kobayashi; Tsuyoshi Tomoyama
- Web page: https://patentgrep.com/patent/US12114490B2

## CPC

- H10B 12/50: {Peripheral circuit region structures}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/488: {Word lines}
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/482: {Bit lines}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An apparatus includes a substrate; a memory cell region provided over the substrate; a peripheral region provided over the substrate and adjacent to the memory cell region; and a plurality of word-lines extending in parallel across the memory cell region and the peripheral region; a first insulating film covering top surfaces of the plurality of word-lines in each of the memory cell region and the peripheral region and covering side surfaces of upper portions of the plurality of word-lines in the peripheral region without covering side surfaces of the upper portions of the plurality of word-lines in the memory cell region.

## Claims

### Claim 1

An apparatus comprising:
a substrate;
a memory cell region provided over the substrate;
a peripheral region provided over the substrate and adjacent to the memory cell region;
a plurality of word-lines extending in parallel across the memory cell region and the peripheral region;
a first insulating film covering top surfaces of the plurality of word-lines in each of the memory cell region and the peripheral region and covering side surfaces of upper portions of the plurality of word-lines in the peripheral region without covering side surfaces of the upper portions of the plurality of word-lines in the memory cell region; and
a third insulating film between the first insulating film and the top surfaces of the plurality of word-lines in the memory cell region.

### Claim 2

An apparatus comprising:
a substrate;
a memory cell region provided over the substrate;
a peripheral region provided over the substrate and adjacent to the memory cell region;
a plurality of word-lines extending in parallel across the memory cell region and the peripheral region;
a first insulating film covering top surfaces of the plurality of word-lines in each of the memory cell region and the peripheral region and covering side surfaces of upper portions of the plurality of word-lines in the peripheral region without covering side surfaces of the upper portions of the plurality of word-lines in the memory cell region; and
a second insulating film over the first insulating film in the peripheral region; and
a plurality of word-line-contacts each connected to a corresponding one of the plurality of word-lines passing through the first and second insulating films in the peripheral region;
wherein each of the plurality of word-line contacts including an upper portion surrounded by the second insulating film and a lower portion surrounded by the first insulating film, and
wherein the lower portion has a smaller diameter than that of the upper portion.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the first insulating film comprises a material different from that of the second insulating film.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the first insulating film comprises silicon nitride, and the second insulating film comprises silicon dioxide.