# US 12,114,489 B2 · Vertical access line in a folded digitline sense amplifier

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- Number: US 12,114,489 B2
- Document ID: US12114489B2
- Status: Granted
- Kind: B2
- Application number: 17/540,589
- Filed: 2021-12-02
- Published: 2023-06-08
- Granted: 2024-10-08
- Earliest claimed: 2021-12-02
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Anton P. Eppich
- Web page: https://patentgrep.com/patent/US12114489B2

## CPC

- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- H10B 12/50: {Peripheral circuit region structures}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present disclosure includes apparatuses and methods for vertical access line in a folded digitline sense amplifier. An example apparatus includes an array of memory cells. The memory cells form active areas having adjacent access devices, each access device having a first source/drain region and a second source/drain region separated by a channel region and a gate opposing the channel region. A pair of adjacent memory cells can share a digitline contact at the second source/drain region. A storage node contact can be coupled to respective first source/drain regions and each gate can be connected to vertically oriented access lines formed on opposing side of a depletion region to each access device. An insulator material can be patterned between adjacent digitlines to isolate adjacent memory cells.

## Claims

### Claim 1

An apparatus, comprising:
an array of memory cells, wherein
the memory cells form active areas having adjacent access devices, each access device having a first source/drain region and a second source/drain region separated by a channel region and a gate opposing the channel region;
a pair of adjacent memory cells share a digitline contact at the respective second source/drain regions and each respective storage node of the pair of adjacent memory cells is coupled to the respective first source/drain regions; and
each gate is connected to vertically oriented access lines formed on opposing side of a depletion region to each access device;
a sense amplifier coupled to digitlines in the array according to a folded digitline sense amplifier architecture; and
an insulator material patterned between adjacent digitlines to isolate adjacent memory cells.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein each memory cell is formed within four lithographic features squared (4F2).

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein each active area is at an angle of a range between 40-50 degrees to an orientation of the vertically oriented access lines and the digitlines.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein each successive active area is alternately angled relative to an adjacent active area.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the memory cells are dynamic random access memory (DRAM) cells.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the vertically oriented access lines and gates are formed using atomic layer deposition techniques.

### Claim 7

An apparatus, comprising:
an array of memory cells, wherein
each memory cell is formed within four lithographic features squared (4F2) according to a folded digitline sense amplifier architecture;
the memory cells include alternately angled active areas having adjacent access devices, each access device having a first source/drain region and a second source/drain region separated by a channel region and a gate opposing the channel region;
a pair of adjacent memory cells share a digitline contact at the respective second source/drain regions and a each respective storage node of the pair of adjacent memory cells is coupled to the respective first source/drain regions; and
the gate is connected to vertically oriented access lines formed on opposing side of a depletion region to each access device;
a sense amplifier coupled to digitlines in the array; and
an insulator material formed between adjacent digitlines to separate adjacent memory cells.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the gate is a conductive spacer.

### Claim 9 (depends on 7)

The apparatus of claim 7, wherein the gate controls current flow between the digitline contact and each access device.

### Claim 10 (depends on 7)

The apparatus of claim 7, wherein each vertically oriented access line passes over alternating active areas.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein each vertically oriented access line activates one memory cell of the pair of adjacent memory cells.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein one of the adjacent digitlines remains at a reference voltage.

### Claim 13 (depends on 7)

The apparatus of claim 7, wherein the gate has an aspect ratio (AR) of the height to width being in a range of from 5:1 to 15:1.

### Claim 14 (depends on 7)

The apparatus of claim 7, wherein the digitline contact is adjacent the depletion region.

### Claim 15

An apparatus, comprising:
a memory cell having a size of four lithographic features squared (4F2);
wherein the memory cell includes a vertical gate opposing a channel region;
wherein the channel region is coupled a storage node at first source/drain region and is coupled to a digitline at a second source/drain region;
wherein an active area of the memory cell is at an angle between 20° and 65° with respect to the digitline;
wherein an insulator material isolates the memory cell from an adjacent memory cell; and
wherein the memory cell is coupled to the digitline having a folded digitline sense amplifier architecture.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the digitline is approximately orthogonal to the vertical gate.

### Claim 17 (depends on 15)

The apparatus of claim 15, the memory cells include two lithographic features (2F) on a vertical axis crossed with two lithographic features on a horizontal axis to produce the memory cell within four lithographic features squared (4F2).

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein the vertical gate is formed above an active area of the memory cell and on a sidewall of a depletion region of the memory cell.