# US 12,114,485 B2 · Semiconductor structure and method for manufacturing same

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- Number: US 12,114,485 B2
- Document ID: US12114485B2
- Status: Granted
- Kind: B2
- Application number: 17/669,573
- Filed: 2022-02-11
- Published: 2023-01-19
- Granted: 2024-10-08
- Earliest claimed: 2021-07-16
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Qinghua Han
- Web page: https://patentgrep.com/patent/US12114485B2

## CPC

- H10B 12/05: {Making the transistor}
- H10B 12/482: {Bit lines}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/488: {Word lines}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/299: {having lateral doping variations (IGFETs having lightly doped source or drain extensions H10D30/601)}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10D 30/6728: {Vertical TFTs}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided are a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a base; a bit line; and a semiconductor channel including a first doped region, a channel region, and a second doped region that are sequentially arranged, where the first doped region contacts the bit line, and the first doped region, the channel region, and the second doped region are doped with first-type doped ions. The channel region is further doped with second-type doped ions, enabling a concentration of majority carriers in the channel region to be less than a concentration of majority carriers in the first doped region and a concentration of majority carriers in the second doped region. The first-type doped ions are one of N-type ions or P-type ions, and the second-type doped ions are the other of N-type ions or P-type ions.

## Claims

### Claim 1

A semiconductor structure, comprising:
a base;
a bit line, located on the base; and
a semiconductor channel, located on a surface of the bit line, wherein in a direction from the base to the bit line, the semiconductor channel comprises a first doped region, a channel region, and a second doped region that are sequentially arranged, wherein the first doped region contacts the bit line, and the first doped region, the channel region, and the second doped region are doped with first-type doped ions, the channel region is further doped with second-type doped ions, enabling a concentration of majority carriers in the channel region to be less than concentrations of majority carriers in the first doped region and the second doped region, the first-type doped ions being one of N-type ions or P-type ions, and the second-type doped ions being the other of N-type ions or P-type ions.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, wherein the second-type doped ions are also located in a region of the first doped region close to the channel region and a region of the second doped region close to the channel region.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, wherein an effective doping concentration of the first-type doped ions in the channel region is less than an effective doping concentration of the first-type doped ions in the first doped region, and the effective doping concentration of the first-type doped ions in the channel region is less than an effective doping concentration of the first-type doped ions in the second doped region.

### Claim 4 (depends on 3)

The semiconductor structure according to claim 3, wherein the effective doping concentration of the first-type doped ions in the channel region is 8×1018 atom/cm3 to 2×1019 atom/cm3.

### Claim 5 (depends on 3)

The semiconductor structure according to claim 3, wherein the effective doping concentration of the first-type doped ions in the first doped region is 3×1019 atom/cm3 to 1×1020 atom/cm3, and the effective doping concentration of the first-type doped ions in the second doped region is 3×1019 atom/cm3 to 1×1020 atom/cm3.

### Claim 6 (depends on 1)

The semiconductor structure according to claim 1, wherein an area of an orthographic projection of the channel region onto the base is smaller than an area of an orthographic projection of the second doped region onto the base and an area of an orthographic projection of the first doped region onto the base.

### Claim 7 (depends on 1)

The semiconductor structure according to claim 1, wherein the base, the bit line, and the semiconductor channel have a same semiconductor element.

### Claim 8 (depends on 7)

The semiconductor structure according to claim 7, wherein a material of the bit line further comprises a metal semiconductor compound.

### Claim 9 (depends on 8)

The semiconductor structure according to claim 8, further comprising: a metal contact layer, located on a top surface of the second doped region away from the base, wherein the metal semiconductor compound and the metal contact layer have a same metal element.

### Claim 10 (depends on 1)

The semiconductor structure according to claim 1, further comprising:
an insulating layer, covering sidewall surfaces of the channel region;
a word line, covering sidewall surfaces of the insulating layer away from the channel region, wherein sidewalls of two adjacent ones of the first doped regions, sidewalls of two adjacent ones of the word lines and sidewalls of adjacent second doped regions define a gap; and
an isolation layer, located in the gap, wherein a top surface of the isolation layer away from the base is not lower than top surfaces of the second doped regions away from the base.

### Claim 11

A method for manufacturing a semiconductor structure, comprising:
providing a base;
forming an initial bit line on the base, and forming a semiconductor channel on a surface of the initial bit line away from the base, wherein in a direction from the base to the initial bit line, the semiconductor channel comprises a first doped region, a channel region, and a second doped region that are sequentially arranged, and are doped with first-type doped ions at a same doping concentration, wherein the first-type doped ions are one of N-type ions or P-type ions;
forming a sacrifice layer doped with second-type doped ions, wherein the sacrifice layer at least covers the sidewall of the channel region, and the second-type doped ions are the other of N-type ions or P-type ions;
diffusing the second-type doped ions into the channel region by an annealing process, to reduce a concentration of majority carriers in the channel region; and
removing the sacrifice layer, to expose the sidewall of the channel region.

### Claim 12 (depends on 11)

The method according to claim 11, wherein a doping concentration of the second-type doped ions in the sacrifice layer is 4×1020 atom/cm3 to 9×1020 atom/cm3.

### Claim 13 (depends on 11)

The method according to claim 11, further comprising: before forming the sacrifice layer doped with second-type doped ions on the sidewall of the channel region,
forming a protection layer on a sidewall surface of the channel region, wherein the protection layer covers the sidewall surface of the channel region; and
further comprising: after removing the sacrifice layer, removing the protection layer.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the sacrifice layer completely fills an interval between two adjacent ones of the protection layers, and is located in an interval between two adjacent ones of the second doped regions.

### Claim 15 (depends on 11)

The method according to claim 11, wherein in the step of the annealing process, a diffusion direction of the second-type doped ions is from the channel region to the first doped region or from the channel region to the second doped region.

### Claim 16 (depends on 11)

The method according to claim 11, further comprising: before forming the sacrifice layer doped with second-type doped ions on the sidewall of the channel region,
forming first isolation layers, each covering sidewall surface of each first doped region, wherein a first interval is provided between first isolation layers on sidewalls of two adjacent ones of the first doped regions on a same initial bit line, and the first interval exposes the initial bit line;
forming a second isolation layer, located in the first interval, a top surface of which away from the base is not lower than a top surface of the second doped region away from the base wherein a second interval is provided between the second isolation layer and the channel region; and
forming a third isolation layer covering a sidewall surface of the second doped region, wherein the third isolation layer contacts the second isolation layer, a third interval is provided between second isolation layers located on sidewalls of two adjacent ones of the second doped regions on two adjacent ones of the initial bit lines, wherein the second interval is in communication with the third interval.

### Claim 17 (depends on 16)

The method according to claim 16, further comprising: after removing the sacrifice layer,
forming an insulating layer covering the sidewall surface of the channel region; and
forming a word line covering a sidewall surface of the insulating layer away from the channel region, wherein the word line and the insulating layer jointly completely fill the second interval.

### Claim 18 (depends on 17)

The method according to claim 17, further comprising: after forming the word line,
removing the second isolation layer and the third isolation layer, to expose the initial bit line; and
metallizing the exposed initial bit line, to form the bit line, wherein a material of the bit line comprises a metal semiconductor compound.

### Claim 19 (depends on 18)

The method according to claim 18, further comprising: after forming the word line and before removing the second isolation layer and the third isolation layer,
forming an initial transition layer on a top surface of the second doped region away from the base by an epitaxial growth process, wherein the initial transition layer is doped with the first-type doped ions, a doping concentration of which in the initial transition layer is greater than an effective doping concentration of the first-type doped ions in the second doped region, and an orthographic projection of the initial transition layer onto the base covers an orthographic projection of the second doped region onto the base.

### Claim 20 (depends on 19)

The method according to claim 19, wherein the step of metallizing the initial bit line further comprises: metallizing the initial transition layer.