# US 12,114,484 B2 · Buried bit line structure, manufacturing method thereof, and semiconductor structure

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- Number: US 12,114,484 B2
- Document ID: US12114484B2
- Status: Granted
- Kind: B2
- Application number: 17/650,702
- Filed: 2022-02-11
- Published: 2023-02-02
- Granted: 2024-10-08
- Earliest claimed: 2021-07-29
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Wei Feng; Jingwen Lu; Bingyu Zhu; Zhaopei Cui
- Web page: https://patentgrep.com/patent/US12114484B2

## CPC

- H10B 12/482: {Bit lines}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a method of manufacturing a buried bit line structure and a buried bit line structure. The method of manufacturing a buried bit line structure includes: providing an initial structure, the initial structure including active region structures; forming an initial bit line trench, the initial bit line trench exposing the active region structure; forming a conductive structure, the conductive structure being located at the bottom of the initial bit line trench; forming a bit line contact structure, the bit line contact structure covering the conductive structure, and a top surface of the bit line contact structure being lower than a top surface of the active region structure; and forming an insulation structure, the insulation structure covering the bit line contact structure.

## Claims

### Claim 1

A method of manufacturing a buried bit line structure, comprising:
providing an initial structure, the initial structure comprising a base and a protective layer provided on the base, and the base comprising active region structures and a dielectric layer, and a top surface of the active region structures is flush with a top surface of the dielectric layer;
forming an initial bit line trench in the initial structure, the initial bit line trench exposing the active region structures;
forming a conductive structure, the conductive structure being located at a bottom of the initial bit line trench and being at a preset distance from a bottom surface of the initial bit line trench;
forming a bit line contact structure, the bit line contact structure covering the conductive structure, and a top surface of the bit line contact structure being lower than the top surface of the active region structures; and
forming an insulation structure, the insulation structure covering the bit line contact structure, and a top surface of the insulation structure being flush with a top surface of the protective layer.

### Claim 2 (depends on 1)

The method of manufacturing a buried bit line structure according to claim 1, further comprising:
forming an initial isolation structure, the initial isolation structure covering a side wall and a bottom wall of the initial bit line trench, and the top surface of the protective layer;
forming an initial barrier structure, the initial barrier structure covering the initial isolation structure; and
forming an initial conductive structure, the initial conductive structure filling the initial bit line trench and covering the initial barrier structure.

### Claim 3 (depends on 2)

The method of manufacturing a buried bit line structure according to claim 2, wherein the forming a conductive structure comprises:
etching back the initial conductive structure to form the conductive structure; and
removing a part of the initial barrier structure, a retained part of the initial barrier structure being flush with a top surface of the conductive structure.

### Claim 4 (depends on 3)

The method of manufacturing a buried bit line structure according to claim 3, further comprising:
removing a part of the initial isolation structure covering the side wall of the initial bit line trench and the top surface of the protective layer, and retaining a second part of the initial isolation structure located on the bottom surface of the initial bit line trench, to form a gap between the conductive structure and the side wall of the initial bit line trench.

### Claim 5 (depends on 4)

The method of manufacturing a buried bit line structure according to claim 4, wherein the forming a bit line contact structure comprises:
depositing the bit line contact structure by a low pressure chemical vapor deposition process, the bit line contact structure sealing an opening of the gap to form an air gap, wherein a top surface of the air gap is defined by the bit line contact structure.

### Claim 6 (depends on 1)

The method of manufacturing a buried bit line structure according to claim 1, wherein the providing an initial structure comprises:
providing a substrate;
etching the substrate to form a plurality of the active region structures arranged in an array;
forming the dielectric layer, the dielectric layer being configured to isolate each of the active region structures;
forming a buried word line, the buried word line being provided in the dielectric layer and the active region structures, wherein the buried word line comprises an insulation portion, the insulation portion extends along a thickness direction of the dielectric layer, and a top surface of the insulation portion is flush with the top surface of the dielectric layer; and
forming the protective layer, the protective layer covering the dielectric layer, the active region structures, and the buried word line of the base.

### Claim 7 (depends on 6)

The method of manufacturing a buried bit line structure according to claim 6, wherein the forming an initial bit line trench comprises:
forming a mask layer, the mask layer covering a part of the protective layer, and the mask layer comprising an opening exposing a part of a region of the protective layer; and
removing a part of the initial structure according to a pattern defined by the mask layer, and exposing a part of a region of the active region structures, the part of the region of the protective layer, and a part of a region of the dielectric layer, and forming the initial bit line trench.

### Claim 8 (depends on 7)

The method of manufacturing a buried bit line structure according to claim 7, wherein the bottom surface of the initial bit line trench is higher than a bottom surface of the insulation portion of the buried word line.

### Claim 9 (depends on 8)

The method of manufacturing a buried bit line structure according to claim 8, wherein along a depth direction of the initial bit line trench, the bottom surface of the initial bit line trench is lower than four-fifths of a height of the insulation portion of the buried word line.

### Claim 10 (depends on 1)

The method of manufacturing a buried bit line structure according to claim 1, further comprising:
removing the protective layer, to expose the insulation structure and the active region structures.

### Claim 11

A buried bit line structure, comprising:
a base, the base comprising active region structures and a dielectric layer, and a top surface of the active region structures is flush with a top surface of the dielectric layer;
a bit line trench, provided in the dielectric layer and the active region structures;
a conductive structure, the conductive structure being located at a bottom of the bit line trench and being at a preset distance from a bottom surface of the bit line trench;
a bit line contact structure, the bit line contact structure covering the conductive structure, and a top surface of the bit line contact structure being lower than the top surface of the active region structures; and
an insulation structure, the insulation structure covering the bit line contact structure.

### Claim 12 (depends on 11)

The buried bit line structure according to claim 11, wherein a top surface of the insulation structure is higher than the top surface of the active region structures.

### Claim 13 (depends on 12)

The buried bit line structure according to claim 12, further comprising:
an isolation structure, the isolation structure covering a part of the bottom surface of the bit line trench and the isolation structure located between the conductive structure and the base; and
a barrier structure, the barrier structure covering a side surface and a bottom surface of the conductive structure.

### Claim 14 (depends on 13)

The buried bit line structure according to claim 13, wherein an air gap is formed between the barrier structure and a side wall of the bit line trench.

### Claim 15 (depends on 11)

The buried bit line structure according to claim 11, wherein the base further comprises a buried word line, and the buried word line is provided in the dielectric layer and the active region structures.

### Claim 16 (depends on 15)

The buried bit line structure according to claim 15, wherein the buried word line extends along a second direction, and the conductive structure extends along a first direction perpendicular to the second direction.

### Claim 17 (depends on 11)

A semiconductor structure, wherein the semiconductor structure comprises the buried bit line structure according to claim 11, the base further comprises a buried word line, and the buried word line is provided in the dielectric layer and the active region structures.

### Claim 18 (depends on 17)

The buried bit line structure according to claim 17, wherein the buried word line comprises an insulation portion, along a depth direction of the bit line trench, the bottom surface of the bit line trench is lower than four-fifths of a height of the insulation portion of the buried word line.

### Claim 19 (depends on 11)

The buried bit line structure according to claim 11, wherein the bit line contact structure covers a part of a side surface of the bit line trench and contacts at least one of the active region structures.

### Claim 20 (depends on 14)

The buried bit line structure according to claim 14, wherein a top surface of the air gap is defined by the bit line contact structure.