# US 12,114,482 B2 · Fabrication method of a memory and the memory

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- Number: US 12,114,482 B2
- Document ID: US12114482B2
- Status: Granted
- Kind: B2
- Application number: 17/403,809
- Filed: 2021-08-16
- Published: 2022-06-30
- Granted: 2024-10-08
- Earliest claimed: 2020-12-30
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Kangshu Zhan; Jun Xia; Qiang Wan; Tao Liu; Sen Li
- Web page: https://patentgrep.com/patent/US12114482B2

## CPC

- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/33: {the capacitor extending under the transistor}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/036: {the capacitor extending under the transistor}
- H10B 12/05: {Making the transistor}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments provide a memory and a fabrication method thereof, and relates to the field of storage device technology to solve the technical problem of lower storage density of the memory. The fabrication method of the memory includes: providing a substrate including a central region and an edge region connected to each other, a first contact structure electrically connected to a wordline structure in the substrate being formed in the edge region; forming a second contact structure electrically connected to the first contact structure on the edge region; forming a capacitor structure electrically connected to the wordline structure on the central region; forming a third contact structure electrically connected to the second contact structure on the second contact structure; and forming a transistor structure electrically connected to the wordline structure on the capacitor structure and the third contact structure.

## Claims

### Claim 1

A fabrication method of a memory, comprising:
providing a substrate, the substrate comprising a central region and an edge region connected to the central region, a first contact structure being formed in the edge region, and the first contact structure being electrically connected to a wordline structure in the substrate;
forming a second contact structure on the edge region, the second contact structure being electrically connected to the first contact structure;
forming a capacitor structure on the central region, the capacitor structure being electrically connected to the wordline structure;
forming a third contact structure on the second contact structure, the third contact structure being electrically connected to the second contact structure; and
forming a transistor structure on the capacitor structure and the third contact structure, the transistor structure being electrically connected to the third contact structure, and an orthographic projection of the transistor structure on the substrate being at least partially coincident with orthographic projections of the capacitor structure and the third contact structure on the substrate.

### Claim 2 (depends on 1)

The fabrication method according to claim 1, wherein before the second contact structure is formed on the edge region, the fabrication method further comprises:
forming a mask layer having a hole structure on the substrate; and
forming a lower electrode layer on an inner surface and a bottom of the hole structure.

### Claim 3 (depends on 2)

The fabrication method according to claim 2, wherein the hole structure comprises a first hole structure and a second hole structure, the first hole structure being positioned on the central region, the second hole structure being positioned on the edge region; and wherein the second hole structure exposes the first contact structure.

### Claim 4 (depends on 3)

The fabrication method according to claim 3, wherein the lower electrode layer comprises a first lower electrode layer and a second lower electrode layer, the first lower electrode layer being arranged in the first hole structure, and the second lower electrode layer being arranged in the second hole structure.

### Claim 5 (depends on 3)

The fabrication method according to claim 3, wherein the substrate further comprises a bitline structure and a capacitor contact structure arranged at intervals, the first hole structure exposing the capacitor contact structure, an end of the capacitor contact structure being electrically connected to the wordline structure, and another end of the capacitor contact structure being connected to the capacitor structure.

### Claim 6 (depends on 4)

The fabrication method according to claim 4, wherein forming a second contact structure on the edge region comprises:
forming a first photoresist layer on the central region, the first photoresist layer covering the first hole structure and a part of the mask layer;
forming a first conductive layer in the second hole structure, the first conductive layer and the second lower electrode layer constituting the second contact structure; and
removing the first photoresist layer.

### Claim 7 (depends on 2)

The fabrication method according to claim 2, wherein forming a mask layer having a hole structure on the substrate comprises:
stacking an initial first insulating layer, an initial first supporting layer, an initial second insulating layer and an initial second supporting layer on the substrate; and
removing, by etching, a part of the initial first insulating layer, a part of the initial first supporting layer, a part of the initial second insulating layer and a part of the initial second supporting layer, to form a first insulating layer having a hole structure, a first supporting layer having a hole structure, a second insulating layer having a hole structure, and a second supporting layer having a hole structure; the first insulating layer, the first supporting layer, the second insulating layer and the second supporting layer constituting the mask layer.

### Claim 8 (depends on 7)

The fabrication method according to claim 7, wherein forming a capacitor structure on the central region comprises:
removing the first insulating layer and the second insulating layer to form a cavity structure;
forming a dielectric layer on a surface of the lower electrode layer;
forming an upper electrode layer on a surface of the dielectric layer; and
forming a second conductive layer on a surface of the upper electrode layer, the second conductive layer filling up the cavity structure and covering the upper electrode layer; and the lower electrode layer, the dielectric layer, the upper electrode layer and the second conductive layer positioned on the central region constituting the capacitor structure.

### Claim 9 (depends on 8)

The fabrication method according to claim 8, wherein forming a third contact structure on the second contact structure comprises:
removing a part of the dielectric layer, a part of the upper electrode layer and a part of the second conductive layer on the edge region to expose the second contact structure;
forming a third insulating layer on the capacitor structure and the second contact structure;
removing a part of the third insulating layer to form a third hole structure that exposes the second contact structure; and
forming a barrier layer and a third conductive layer in the third hole structure, the barrier layer and the third conductive layer constituting the third contact structure.

### Claim 10 (depends on 9)

The fabrication method according to claim 9, wherein forming a transistor structure on the substrate comprises:
depositing a polysilicon layer, an oxide layer and a gate layer in sequence on the third insulating layer, the polysilicon layer covering the third insulating layer and the third contact structure;
removing a part of the oxide layer and a part of the gate layer to expose a part of the polysilicon layer, the remained oxide layer forming a gate oxide layer, and the remained gate layer forming a gate structure;
doping ions into the polysilicon layer by means of an ion implantation technology to form a source structure and a drain structure; and
forming a gate protection layer on the polysilicon layer, the source structure, the drain structure, the gate oxide layer, the gate structure and the gate protection layer constituting the transistor structure.

### Claim 11 (depends on 10)

The fabrication method according to claim 10, wherein after the transistor structure is formed on the substrate, the fabrication method further comprises:
forming a fourth contact structure, a fifth contact structure and a sixth contact structure arranged at intervals on the capacitor structure and the transistor structure, the fourth contact structure being electrically connected to the capacitor structure, the fifth contact structure being electrically connected to the source structure or the drain structure, and the sixth contact structure being electrically connected to the gate structure.

### Claim 12

A memory, comprising:
a substrate, the substrate comprising a central region and an edge region connected to the central region, a first contact structure being formed in the edge region, and the first contact structure being electrically connected to a wordline structure in the substrate;
a capacitor structure, arranged on the central region and electrically connected to the wordline structure;
a second contact structure, arranged on the edge region and electrically connected to the first contact structure;
a third contact structure, arranged on the second contact structure and electrically connected to the second contact structure; and
a transistor structure, arranged on the capacitor structure and the third contact structure;
wherein the transistor structure is electrically connected to the third contact structure, and an orthographic projection of the transistor structure on the substrate is at least partially coincident with orthographic projections of the capacitor structure and the third contact structure on the substrate.

### Claim 13 (depends on 12)

The memory according to claim 12, wherein the transistor structure comprises a source structure and a drain structure formed in a polysilicon layer, a gate oxide layer formed on the polysilicon layer, a gate structure formed on the gate oxide layer, and a gate protection layer covering the gate oxide layer and the gate structure.

### Claim 14 (depends on 13)

The memory according to claim 13, wherein the memory further comprises a fourth contact structure, a fifth contact structure and a sixth contact structure arranged at intervals;
the fourth contact structure being electrically connected to the capacitor structure, the fifth contact structure being electrically connected to the source structure or the drain structure of the transistor structure, and the sixth contact structure being electrically connected to the gate structure of the transistor structure.

### Claim 15 (depends on 12)

The memory according to claim 12, wherein the substrate further comprises a bitline structure and a capacitor contact structure arranged at intervals, an end of the capacitor contact structure is electrically connected to the wordline structure, and another end of the capacitor contact structure is connected to the capacitor structure.