# US 12,114,480 B2 · Method of making of plurality of 3D vertical logic elements integrated with 3D memory

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- Number: US 12,114,480 B2
- Document ID: US12114480B2
- Status: Granted
- Kind: B2
- Application number: 17/558,490
- Filed: 2021-12-21
- Published: 2023-06-22
- Granted: 2024-10-08
- Earliest claimed: 2021-12-21
- Assignees: Tokyo Electron Limited
- Applicants: Tokyo Electron Limited
- Inventors: H. Jim Fulford; Mark I. Gardner; Partha Mukhopadhyay
- Web page: https://patentgrep.com/patent/US12114480B2

## CPC

- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10D 1/714: {having horizontal extensions}
- H10B 12/033: {the capacitor extending over the transistor}
- H10B 12/05: {Making the transistor}
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/716: {having vertical extensions}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Apparatuses, devices, and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

## Claims

### Claim 1

A memory, comprising:
a first portion including a transistor, the first portion including:
a first source/drain structure extending horizontally;
a gate structure above the first source/drain structure and extending horizontally;
a second source/drain structure above the gate structure and extending horizontally, each of the structures separated from each other by at least one dielectric; and
a semiconductor material extending from the first source/drain structure to the second source/drain structure;
a second portion including a capacitor electrically coupled to and extending from the transistor.

### Claim 2 (depends on 1)

The memory of claim 1, wherein the capacitor and the transistor are each vertically aligned with the semiconductor material.

### Claim 3 (depends on 1)

The memory of claim 1, wherein the semiconductor material extends through the second portion.

### Claim 4 (depends on 1)

The memory of claim 1, wherein the first portion is adjacent the substrate, the second portion is adjacent the first portion, and the first portion and the second portion are vertically aligned.

### Claim 5 (depends on 1)

The memory of claim 1, wherein the capacitor includes:
a first metal part having an interior cavity; and
a second metal part at least partly formed inside of the interior cavity of the first metal part.

### Claim 6 (depends on 5)

The memory of claim 5, further comprising a layer of electrically insulating material disposed between the first metal part and the second metal part.

### Claim 7 (depends on 1)

The memory of claim 1, further comprising:
a first metal part of the capacitor in electrical contact with the transistor; and
a second metal part of the capacitor in electrical contact with an electrical common or a ground.

### Claim 8

A method of fabricating a memory device including a transistor, the method comprising:
forming a stack of layers for the transistor including:
a first source/drain structure of the transistor;
a gate structure of the transistor, the gate structure being above the first source/drain structure and extending horizontally; and
a second source/drain structure of the transistor, each of the structures separated from each other by at least one dielectric;
forming a cavity through the stack of layers;
forming a semiconductor material in a first portion of the cavity, the semiconductor material extending from the first source/drain structure to the second source/drain structure; and
forming a capacitor electrically coupled to and extending from the transistor in a second portion of the cavity.

### Claim 9 (depends on 8)

The method of claim 8, wherein the capacitor and the transistor are each vertically aligned with the cavity.

### Claim 10 (depends on 8)

The method of claim 8, wherein the transistor includes a doped silicon material.

### Claim 11 (depends on 8)

The method of claim 8, wherein the semiconductor material extends continuously through the first portion and the second portion of the cavity.

### Claim 12 (depends on 8)

The method of claim 8, further comprising:
forming a first metal part of the capacitor;
forming an interior cavity in the first metal part; and
forming a second metal part at least partialy formed inside of the interior cavity of the first metal part.

### Claim 13 (depends on 12)

The method of claim 12, further comprising forming a layer of electrically insulating material disposed between the first metal part and the second metal part.

### Claim 14 (depends on 8)

The method of claim 8, further comprising:
forming a first metal part of the capacitor in electrical contract with the transistor; and
forming a second metal part of the capacitor in electrical contact with an electrical common or ground.

### Claim 15

A system comprising:
a column extending from a substrate, the column comprising:
a transistor having a channel extending vertically along the column;
a capacitor substantially vertically aligned with the transistor and having a length that is greater than a width of the capacitor, the capacitor including:
a first metal part in electrical contact with the transistor and defining an interior cavity;
a second metal part at least partly disposed inside of the interior cavity of the first metal part and in an electrical contact with an electrical common or a ground, the first metal part oriented vertically aligned with the transistor; and
a layer of electrically insulating material disposed inside the interior cavity in between the first metal part and the second metal part.

### Claim 16 (depends on 15)

The system of claim 15, further comprising a second dielectric material layer electrically insulating a source/drain of the transistor from the substrate.

### Claim 17 (depends on 15)

The system of claim 15, further comprising a layer of silicide disposed between a doped region of the transistor and the first metal part.

### Claim 18 (depends on 15)

The system of claim 15, further comprising a first metal contact forming a first source/drain of the transistor, a second metal contact forming a gate of the transistor, and a third metal contact forming a second source/drain of the transistor.

### Claim 19 (depends on 15)

The system of claim 15, further comprising an electrical contact between a first source/drain region of the transistor and the first metal part of the capacitor.

### Claim 20 (depends on 19)

The system of claim 19, further comprising the first source/drain region of the transistor vertically aligned with a second source/drain region of the transistor.