# US 12,114,437 B2 · Wiring structure, method for manufacturing same, and semiconductor package

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- Number: US 12,114,437 B2
- Document ID: US12114437B2
- Status: Granted
- Kind: B2
- Application number: 17/926,710
- Filed: 2021-06-23
- Published: 2023-06-29
- Granted: 2024-10-08
- Earliest claimed: 2020-06-24
- Assignees: Resonac Corporation
- Applicants: Showa Denko Materials Co., Ltd.
- Inventors: Masaya Toba; Kazuyuki Mitsukura
- Web page: https://patentgrep.com/patent/US12114437B2

## CPC

- H05K 3/381: {by special treatment of the substrate}
- H10W 70/685: comprising multiple insulating layers
- H05K 1/09: Use of materials for the {conductive, e.g. } metallic pattern
- H05K 3/18: using precipitation techniques to apply the conductive material
- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- H05K 3/4661: {Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor (other insulating materials H05K3/387)}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/695: Organic materials
- H05K 3/108: {by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241)}
- H05K 2201/032: Materials
- H05K 2203/0723: Electroplating, e.g. finish plating
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed is a method for manufacturing a wiring structure including a step of forming a wiring on an insulating resin layer. The step of forming the wiring includes: forming a modified region including pores in a surface layer of the insulating resin layer by treating a surface of the insulating resin layer with a treatment method including surface modification; forming a seed layer on the surface of the insulating resin layer by sputtering; and forming the wiring on the seed layer by electrolytic copper plating.

## Claims

### Claim 1

A wiring structure, comprising: an insulating resin layer; a seed layer provided on the insulating resin layer and including one or more metal layers; and a copper wiring provided on the seed layer, wherein a modified region including pores is formed in a surface layer of the insulating resin layer on the seed layer side, and a part of metal forming the seed layer penetrates into the pores, and wherein the surface of the insulating resin layer including the modified region has a surface roughness Ra of 70 nm or less.

### Claim 2 (depends on 1)

The wiring structure according to claim 1, wherein the seed layer includes: an adhesion layer in contact with the insulating resin layer; and a power supply layer formed on the adhesion layer, the adhesion layer is a metal layer containing titanium, chromium, tungsten, nickel, or a combination thereof, and the power supply layer is a metal layer containing copper.

### Claim 3 (depends on 1)

The wiring structure according to claim 1, wherein a depth of the modified region is 50 nm or more.

### Claim 4 (depends on 1)

The wiring structure according to claim 1, wherein the wiring includes a linear portion having a width of 1 to 10 μm.

### Claim 5 (depends on 1)

A semiconductor package, comprising: the wiring structure according to claim 1; and a semiconductor chip connected to the wiring of the wiring structure.

### Claim 6

A wiring structure, comprising: an insulating resin layer; a seed layer provided on the insulating resin layer and including one or more metal layers; and a copper wiring provided on the seed layer, wherein a modified region including pores is formed in a surface layer of the insulating resin layer on the seed layer side, and a part of metal forming the seed layer penetrates into the pores, and wherein a depth of the modified region is 50 nm or more and 200 nm or less.

### Claim 7 (depends on 6)

The wiring structure according to claim 6, wherein the seed layer includes: an adhesion layer in contact with the insulating resin layer; and a power supply layer formed on the adhesion layer, the adhesion layer is a metal layer containing titanium, chromium, tungsten, nickel, or a combination thereof, and the power supply layer is a metal layer containing copper.

### Claim 8 (depends on 6)

The wiring structure according to claim 6, wherein the wiring includes a linear portion having a width of 1 to 10 μm.

### Claim 9 (depends on 6)

A semiconductor package, comprising: the wiring structure according to claim 6; and a semiconductor chip connected to the wiring of the wiring structure.