# US 12,114,416 B2 · Heat removal from silicon photonics chip using a recessed side-by-side thermal dissipation layout > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,114,416 B2 - Document ID: US12114416B2 - Status: Granted - Kind: B2 - Application number: 17/517,693 - Filed: 2021-11-03 - Published: 2022-02-24 - Granted: 2024-10-08 - Earliest claimed: 2019-05-07 - Assignees: Mellanox Technologies, Ltd. - Applicants: Mellanox Technologies, Ltd. - Inventors: Elad Mentovich; Anna Sandomirsky; Dimitrios Kalavrouziotis - Web page: https://patentgrep.com/patent/US12114416B2 ## CPC - H05K 1/0206: {by printed thermal vias} - H05K 1/0298: {Multilayer circuits} - H05K 1/183: associated with components mounted in and supported by recessed areas of the PCBs - H05K 3/30: Assembling printed circuits with electric components, e.g. with resistors - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 40/28: comprising Peltier coolers - H10N 10/13: characterised by the heat-exchanging means at the junction - H10W 70/68: Shapes or dispositions thereof - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A semiconductor device assembly (10) includes a multi-layer printed circuit board (PCB—40), a thermoelectric cooler (TEC—30), a chip (22), and packaged integrated circuitry (IC—26). The multi-layer PCB includes a lateral heat conducting path (60) formed in a recessed area (44) of the PCB. The TEC and the chip are disposed on the PCB, side-by-side to one another over the lateral heat conducting path. The TEC is configured to evacuate heat from the chip via the lateral heat conducting path, and to dissipate the evacuated heat via a first end of a heat sink (33) in thermal contact with the TEC. The packaged IC is disposed on an un-recessed area of the PCB, wherein the packaged IC is configured to dissipate heat via a second end of the heat sink that is in thermal contact with the packaged IC. ## Claims ### Claim 1 A semiconductor device assembly, comprising: a multi-layer printed circuit board (PCB) comprising a lateral heat conducting path formed in a recessed area of the PCB; a thermoelectric cooler (TEC) and a chip disposed on the PCB, side-by-side to one another within the recessed area, such that entire bottom surfaces of both the chip and the TEC are mounted directly on the lateral heat conducting path, wherein the TEC is configured to evacuate heat from the chip via the lateral heat conducting path, and to dissipate the evacuated heat via a first end of a heat sink in thermal contact with the TEC; and packaged integrated circuitry (IC) disposed on an un-recessed area of the PCB, wherein the packaged IC is configured to dissipate heat via a second end of the heat sink that is in thermal contact with the packaged IC. ### Claim 2 (depends on 1) The assembly according to claim 1, wherein the chip comprises a silicon photonics (SiPh) chip. ### Claim 3 (depends on 1) The assembly according to claim 1, wherein the lateral heat conducting path comprises heat conducting layers of the PCB, which are in thermal contact with an external surface of the heat conducting path via vertical heat conducting channels. ### Claim 4 (depends on 3) The assembly according to claim 3, wherein the vertical heat conducting channels of the PCB are filled with thermally conductive material. ### Claim 5 (depends on 1) The assembly according to claim 1, wherein the lateral heat conducting path is thermally isolated from the IC. ### Claim 6 (depends on 1) The assembly according to claim 1, wherein the heat sink is attached to a top side of the TEC and to a top side of the packaged IC, wherein the top sides of the TEC and the packaged IC are laterally separated by at least a lateral size of the chip. ### Claim 7 (depends on 1) The assembly according to claim 1, and comprising a control circuit configured to adaptively control the TEC based on an operating power of the chip. ### Claim 8 (depends on 1) The assembly according to claim 1, wherein the chip comprises one or more optical components, and comprising a control circuit configured to control one or more operating wavelengths of the one or more optical components by adaptively controlling the TEC. ### Claim 9 (depends on 8) The assembly according to claim 8, wherein the chip comprises a temperature sensor, and wherein the control circuit is configured to control the one or more operating wavelengths by obtaining a reading of the temperature sensor and controlling the TEC based on the reading. ### Claim 10 (depends on 8) The assembly according to claim 8, wherein, by controlling the TEC, the control circuit is configured to tune an operating wavelength range of the one or more optical components. ### Claim 11 (depends on 8) The assembly according to claim 8, wherein the chip comprises one or more temperature-control devices, and wherein the control circuit is configured to control the one or more operating wavelengths by controlling both the TEC and the one or more temperature-control devices. ### Claim 12 (depends on 11) The assembly according to claim 11, wherein the one or more temperature-control devices are configured to control one or more temperatures of one or more respective optical components associated with one or more respective communication channels, and wherein the control circuit is configured to individually tune the one or more operating wavelengths of the one or more respective communication channels by controlling the one or more respective temperature-control devices. ### Claim 13 A manufacturing method, comprising: forming in a recessed area of a multi-layer printed circuit board (PCB) a lateral heat conducting path; disposing on the PCB a thermoelectric cooler (TEC) and a chip, side-by-side to one another within the recessed area, such that entire bottom surfaces of both the chip and the TEC are mounted directly on the lateral heat conducting path, wherein the TEC is configured to evacuate heat from the chip via the lateral heat conducting path, and to dissipate the evacuated heat via a first end of a heat sink in thermal contact with the TEC; and disposing on an un-recessed area of the PCB packaged integrated circuitry (IC), wherein the packaged IC is configured to dissipate heat via a second end of the heat sink that is in thermal contact with the packaged IC. ### Claim 14 (depends on 13) The manufacturing method according to claim 13, wherein the chip comprises a silicon photonics (SiPh) chip. ### Claim 15 (depends on 13) The manufacturing method according to claim 13, wherein forming the lateral heat conducting path comprises forming thermal contact via vertical heat conducting channels between heat conducting layers of the PCB and an external surface of the heat conducting path. ### Claim 16 (depends on 10) The manufacturing method according to claim 10, and comprising filling the vertical heat conducting channels of the PCB with thermally conductive material. ### Claim 17 (depends on 13) The manufacturing method according to claim 13, wherein the lateral heat conducting path is thermally isolated from the IC. ### Claim 18 (depends on 13) The manufacturing method according to claim 13, wherein the heat sink is attached to a top side of the TEC and to a top side of the packaged IC, and wherein the top sides of the TEC and the packaged IC are laterally separated by at least a lateral size of the chip.