# US 12,113,915 B2 · Federal Information Processing Standard (FIPS) compliant Device Identifier Composition Engine (DICE) certificate chain architecture for embedded systems

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- Number: US 12,113,915 B2
- Document ID: US12113915B2
- Status: Granted
- Kind: B2
- Application number: 17/709,274
- Filed: 2022-03-30
- Published: 2022-10-06
- Granted: 2024-10-08
- Earliest claimed: 2022-03-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Xiaoyu Ruan; Ned M. Smith; Matthew G. Pirretti
- Web page: https://patentgrep.com/patent/US12113915B2

## CPC

- H04L 9/0866: {involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics}
- H04L 9/3252: {using DSA or related signature schemes, e.g. elliptic based signatures, ElGamal or Schnorr schemes}
- H04L 9/0869: {involving random numbers or seeds}
- H04L 9/3066: {involving algebraic varieties, e.g. elliptic or hyper-elliptic curves}
- H04L 9/3263: {involving certificates, e.g. public key certificate [PKC] or attribute certificate [AC]; Public key infrastructure [PKI] arrangements (network architectures or network communication protocols for supporting authentication of entities using certificates in a packet data network H04L63/0823)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Methods and apparatus relating to a Federal Information Processing Standard (FIPS) compliant Device Identifier Composition Engine (DICE) certificate chain architecture for embedded systems are described. In an embodiment, Deterministic Random Bit Generator (DRBG) logic circuitry generates a random number for each layer of a Device Identifier Composition Engine (DICE). The DRBG logic circuitry is a Federal Information Processing Standard (FIPS) approved DRBG logic circuitry. Logic circuitry derives an Elliptic Curve Digital Signature Algorithm (ECDSA) private key for a layer of the DICE based at least in part on one or more operations of a FIPS-approved ECDSA key pair generation logic circuitry. Other embodiments are also disclosed and claimed.

## Claims

### Claim 1

An apparatus comprising:
Deterministic Random Bit Generator (DRBG) logic circuitry to generate a random number for each layer of a Device Identifier Composition Engine (DICE), wherein the DRBG logic circuitry is a Federal Information Processing Standard (FIPS) approved DRBG logic circuitry; and
derivative logic circuitry to derive an Elliptic Curve Digital Signature Algorithm (ECDSA) private key for a layer of the DICE based at least in part on one or more operations of a FIPS-approved ECDSA key pair generation logic circuitry,
wherein at least one certificate chain on an embedded system is to be constructed to link a secure state and transition to a specific attestation key for the layer.

### Claim 2 (depends on 1)

The apparatus of claim 1, comprising logic circuitry to generate a certificate for the layer based at least in part on the private key.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the certificate is to be generated based at least in part on a combine function or a personalization string.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the combine function is to combine the random number with a Compound Device Identifier (CDI).

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the CDI is to be derived from a Unique Device Secret (UDS).

### Claim 6 (depends on 3)

The apparatus of claim 3, wherein the DRBG logic circuitry is to generate the random number based at least in part on the personalization string.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the FIPS-approved ECDSA key pair generation logic circuitry is to generate a key pair, wherein the key pair comprises the ECDSA private key.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising a plurality of DRBG logic circuitry to generate a plurality of random numbers, wherein each of the random numbers is to correspond to a separate layer of the DICE.

### Claim 9 (depends on 1)

The apparatus of claim 1, comprising logic circuitry to generate a CDI for at least one layer of the DICE.

### Claim 10 (depends on 1)

The apparatus of claim 1, further comprising a Non-Volatile Memory (NVM) device to store the random number.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the NVM device comprises one or more of: a Serial Peripheral Interface (SPI) flash and one or more field programmable fuses.

### Claim 12 (depends on 1)

The apparatus of claim 1, further comprising an NVM device to store the random number at a first boot.

### Claim 13 (depends on 1)

The apparatus of claim 1, further comprising an NVM device to store the random number at a first boot, wherein the random number stored in the NVM is to be accessed for any future power cycles.

### Claim 14 (depends on 1)

The apparatus of claim 1, wherein the DICE is a Trusted Computing Group (TCG) DICE.

### Claim 15

A method comprising:
generating, at Deterministic Random Bit Generator (DRBG) logic circuitry, a random number for each layer of a Device Identifier Composition Engine (DICE), wherein the DRBG logic circuitry is a Federal Information Processing Standard (FIPS) approved DRBG logic circuitry;
deriving, at derivative logic circuitry, an Elliptic Curve Digital Signature Algorithm (ECDSA) private key for a layer of the DICE based at least in part on one or more operations of a FIPS-approved ECDSA key pair generation logic circuitry; and
constructing at least one certificate chain on an embedded system to link a secure state and transition to a specific attestation key for the layer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising generating a certificate for the layer based at least in part on the private key.

### Claim 17 (depends on 15)

The method of claim 15, further comprising generating a CDI for at least one layer of the DICE.

### Claim 18 (depends on 15)

The method of claim 15, further comprising generating a plurality of random numbers, wherein each of the random numbers is to correspond to a separate layer of the DICE.

### Claim 19

One or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to cause:
Deterministic Random Bit Generator (DRBG) logic circuitry to generate a random number for each layer of a Device Identifier Composition Engine (DICE), wherein the DRBG logic circuitry is a Federal Information Processing Standard (FIPS) approved DRBG logic circuitry; and
derivative logic circuitry to derive an Elliptic Curve Digital Signature Algorithm (ECDSA) private key for a layer of the DICE based at least in part on one or more operations of a FIPS-approved ECDSA key pair generation logic circuitry; and
construction of at least one certificate chain on an embedded system to link a secure state and transition to a specific attestation key for the layer.

### Claim 20 (depends on 19)

The one or more computer-readable media of claim 19, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause generation of a certificate for the layer based at least in part on the private key.

### Claim 21 (depends on 19)

The one or more computer-readable media of claim 19, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause generation of a certificate for the layer based at least in part on the private key.

### Claim 22 (depends on 19)

The one or more computer-readable media of claim 19, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause generation of a CDI for at least one layer of the DICE.

### Claim 23 (depends on 19)

The one or more computer-readable media of claim 19, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause generation of a plurality of random numbers, wherein each of the random numbers is to correspond to a separate layer of the DICE.

### Claim 24

An apparatus comprising:
Deterministic Random Bit Generator (DRBG) logic circuitry to generate a random number for each layer of a Device Identifier Composition Engine (DICE), wherein the DRBG logic circuitry is a Federal Information Processing Standard (FIPS) approved DRBG logic circuitry; and
derivative logic circuitry to derive an Elliptic Curve Digital Signature Algorithm (ECDSA) private key for a layer of the DICE based at least in part on one or more operations of a FIPS-approved ECDSA key pair generation logic circuitry,
wherein a plurality of DRBG logic circuitry is to generate a plurality of random numbers, wherein each of the random numbers is to correspond to a separate layer of the DICE.

### Claim 25 (depends on 24)

The apparatus of claim 24, comprising logic circuitry to generate a certificate for the layer based at least in part on the private key.

### Claim 26 (depends on 24)

The apparatus of claim 24, comprising logic circuitry to construct at least one certificate chain on an embedded system to link a secure state and transition to a specific attestation key for the layer.