# US 12,113,896 B1 · End-to-end hardware acceleration for ZKP from witness generation to proof generation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,896 B1 - Document ID: US12113896B1 - Status: Granted - Kind: B1 - Application number: 18/525,604 - Filed: 2023-11-30 - Granted: 2024-10-08 - Earliest claimed: 2023-06-08 - Assignees: Auradine, Inc. - Applicants: Auradine, Inc. - Inventors: Patrick Xu; Minglei Wang; Sidong Li; De Vu; Saptadeep Pal; Lei Chang - Web page: https://patentgrep.com/patent/US12113896B1 ## CPC - H04L 9/088: {Usage controlling of secret information, e.g. techniques for restricting cryptographic keys to pre-authorized uses, different access levels, validity of crypto-period, different key- or password length, or different strong and weak cryptographic algorithms (network architectures or network communication protocols for using time-dependent keys in a packet data network H04L63/068)} - H04L 9/3218: {using proof of knowledge, e.g. Fiat-Shamir, GQ, Schnorr, ornon-interactive zero-knowledge proofs} - G06F 21/602: {Providing cryptographic facilities or services} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A local buffer is integrated with a witness generator and a proof generator on a cryptographic processor and is separate from host memory accessed by a host processor operating with the cryptographic processor in a proving computing system. The witness generator: receives, from software program running on the host processor, compiled code of a zero-knowledge-proof (ZKP) program and specific input to the ZKP program; executes the ZKP program by way of executing the compiled code; records specific output generated from the ZKP program with the specific input, intermediate variable values, and the specific input, as a specific witness of executing the ZKP program; stores the specific witness in the local buffer. The proof generator: receives, from the software program running on the host processor, a proving key; accesses the specific witness in the local buffer; generates a specific zero-knowledge proof for executing the ZKP program with the specific input. ## Claims ### Claim 1 A proving computing system comprising: a host processor; a cryptographic engine that includes a witness generator, a proof generator and a local witness buffer on a semiconductor device, the cryptographic engine is separate from the host processor wherein the local witness buffer in the cryptographic engine is separate from host memory accessed by the host processor; wherein the witness generator in the cryptographic engine (a) receives, from the host processor, compiled code of a cryptographic program and specific input to the cryptographic program, (b) executes the cryptographic program by way of executing the compiled code, (c) records specific output generated from the cryptographic program, intermediate variable values, and the specific input, as a specific witness of executing the cryptographic program, and (d) stores the specific witness in the local witness buffer in the cryptographic engine; wherein the specific witness has a data size exceeding a maximum supported memory access bandwidth of the host memory for a single clock cycle; wherein the proof generator in the cryptographic engine (e) receives, from the host processor, a proving key that was generated along with a verification key, (f) accesses the specific witness in the local witness buffer in the cryptographic engine, wherein the specific witness is accessed in its entirety by the proof generator over first clock cycles fewer than second clock cycles over which the host memory stored data of the same data size is accessed from the host memory and (g) generates a specific proof for executing the cryptographic program with a combination of the proving key, the specific witness and the specific input; wherein a recipient computing system that receives the verification key and the specific proof validates the specific proof with the verification key. ### Claim 2 (depends on 1) The proving computing system of claim 1, wherein the verification key is generated concurrently with the proving key in a trusted setup. ### Claim 3 (depends on 1) The proving computing system of claim 1, wherein the cryptographic program accesses private data not shared by the proving computing system with other computing systems including one or more verifier computing systems that validate the specific proof. ### Claim 4 (depends on 1) The proving computing system of claim 1, wherein the compiled code defines a circuit formed by a plurality of gates derived from the compiled code. ### Claim 5 (depends on 1) The proving computing system of claim 1, wherein the cryptographic engine comprises a plurality of computation logics for performing parallel computations relating to one or more of: fast Fourier transformation, number theoretic transformation, or multi-scalar multiplication. ### Claim 6 (depends on 1) The proving computing system of claim 1, wherein the cryptographic engine is implemented as one of: a single semiconductor device, a single integrated circuit, or a single semiconductor chip that includes one or more chiplets. ### Claim 7 (depends on 1) The proving computing system of claim 1, wherein the cryptographic engine is a zero-knowledge-proof (ZKP) program. ### Claim 8 A cryptographic engine comprising: a witness generator; a proof generator; and a local witness buffer; wherein the local witness buffer is integrated with the witness generator and the proof generator on the cryptographic engine and the local witness buffer is separate from host memory accessed by a host processor operating with the cryptographic engine in a proving computing system; wherein the cryptographic engine combines the witness generator, the proof generator and the local witness buffer into a semiconductor device, the cryptographic engine is separate from the host processor; wherein the witness generator in the cryptographic engine (a) receives, from the host processor, compiled code of a cryptographic program and specific input to the cryptographic program, (b) executes the cryptographic program by way of executing the compiled code, (c) records specific output generated from the cryptographic program, intermediate variable values, and the specific input, as a specific witness of executing the cryptographic program, and (d) stores the specific witness in the local witness buffer in the cryptographic engine; wherein the specific witness has a data size exceeding a maximum supported memory access bandwidth of the host memory for a single clock cycle; wherein the proof generator in the cryptographic engine (e) receives, from the host processor, a proving key that was generated along with a verification key, (f) accesses the specific witness in the local witness buffer in the cryptographic engine, wherein the specific witness is accessed in its entirety by the proof generator over first clock cycles fewer than second clock cycles over which the host memory stored data of the same data size is accessed from the host memory and (g) generates a specific proof for executing the cryptographic program with a combination of the proving key, the specific witness and the specific input; wherein a recipient computing system that receives the verification key and the specific proof validates the specific proof with the verification key. ### Claim 9 (depends on 8) The cryptographic engine of claim 8, wherein the verification key is generated concurrently with the proving key in a trusted setup. ### Claim 10 (depends on 8) The cryptographic engine of claim 8, wherein the cryptographic program accesses private data not shared by the proving computing system with other computing systems including one or more verifier computing systems that validate the specific proof. ### Claim 11 (depends on 8) The cryptographic engine of claim 8, wherein the compiled code defines a circuit formed by a plurality of gates derived from the compiled code. ### Claim 12 (depends on 8) The cryptographic engine of claim 8, wherein the cryptographic engine comprises a plurality of computation logics for performing parallel computations relating to one or more of: fast Fourier transformation, number theoretic transformation, or multi-scalar multiplication. ### Claim 13 (depends on 8) The cryptographic engine of claim 8, wherein the cryptographic engine is implemented as one of: a single semiconductor device, a single integrated circuit, or a single semiconductor chip that includes one or more chiplets. ### Claim 14 (depends on 8) The cryptographic engine of claim 8, wherein the cryptographic program is a zero-knowledge-proof (ZKP) program. ### Claim 15 A method comprising: wherein a local witness buffer in a cryptographic processor is separate from host memory, the local witness buffer accessed by a host processor operating with the cryptographic processor in a proving computing system; wherein the cryptographic processor combines a witness generator, a proof generator and the local witness buffer into a semiconductor device, the cryptographic processor is separate from the host processor; receiving, by the witness generator from the host processor, compiled code of a cryptographic program and specific input to the cryptographic program; executing, by the witness generator, the cryptographic program by way of executing the compiled code; recording, by the witness generator, specific output generated from the cryptographic program, intermediate variable values, and the specific input, as a specific witness of executing the cryptographic program; storing, by the witness generator, the specific witness in the local witness buffer; wherein the specific witness has a data size exceeding a maximum supported memory access bandwidth of the host memory for a single clock cycle; receiving, by the proof generator from the host processor, a proving key that was generated along with a verification key; accessing, by the proof generator, the specific witness in the local witness buffer, wherein the specific witness is accessed in its entirety by the proof generator over first clock cycles fewer than second clock cycles over which host memory stored data of the same data size is accessed from the host memory; generating, by the proof generator, a specific proof for executing the cryptographic program with a combination of the proving key, the specific witness and the specific input; causing a recipient computing system that receives the verification key and the specific proof to validate the specific proof with the verification key. ### Claim 16 (depends on 15) The method of claim 15, wherein the verification key is generated concurrently with the proving key in a trusted setup. ### Claim 17 (depends on 15) The method of claim 15, wherein the cryptographic program accesses private data not shared by the proving computing system with other computing systems including one or more verifier computing systems that validate the specific proof. ### Claim 18 (depends on 15) The method of claim 15, wherein the compiled code defines a circuit formed by a plurality of gates derived from the compiled code. ### Claim 19 (depends on 15) The method of claim 15, wherein the cryptographic processor comprises a plurality of computation logics for performing parallel computations relating to one or more of: fast Fourier transformation, number theoretic transformation, or multi-scalar multiplication. ### Claim 20 (depends on 15) The method of claim 15, wherein the cryptographic processor is implemented as one of: a single semiconductor device, a single integrated circuit, or a single semiconductor chip that includes one or more chiplets. ### Claim 21 (depends on 15) The method of claim 15, wherein the cryptographic program is a zero-knowledge-proof (ZKP) program.