# US 12,113,708 B2 · Provisioning memory resources on flexible hardware platforms > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,708 B2 - Document ID: US12113708B2 - Status: Granted - Kind: B2 - Application number: 17/704,103 - Filed: 2022-03-25 - Published: 2023-09-28 - Granted: 2024-10-08 - Earliest claimed: 2022-03-25 - Assignees: Arista Networks, Inc. - Applicants: Arista Networks, Inc. - Inventors: Maxime Daniel Lorrillere; Suhas Raghunath Joshi - Web page: https://patentgrep.com/patent/US12113708B2 ## CPC - H04L 45/66: {Layer 2 routing, e.g. in Ethernet based MAN's} - H04L 45/42: Centralised routing - H04L 47/762: triggered by the network - H04L 47/781: {Centralised allocation of resources} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A method of allocating programmable memory in a network device includes receiving a set of desired features for the network device, and determining a plurality of constraints associated with the set of desired features. The plurality of constraints are converted into a plurality of Boolean representations of the constraints, and a feasibility is evaluated for the desired features based on the plurality of constraints. ## Claims ### Claim 1 A method of allocating programmable memory in a network device the method comprising: receiving a set of desired features for the network device, wherein the set of desired features is supported by a set of tables to be stored across a plurality of memory banks of the programmable memory; determining a plurality of constraints associated with the set of desired features and the programmable memory; converting the plurality of constraints into a plurality of Boolean representations of the constraints wherein the plurality of Boolean representations of the constraints comprises Boolean representations each representing a state of memory allocation of one or more memory banks in the plurality of memory banks to a corresponding table in the set of tables; using a Satisfiability Modulo Theories (SMT) solver to generate a result by evaluating a feasibility of allocating the programmable memory for the desired features based on the Boolean representations of the constraints, wherein the result generated using the SMT solver indicates whether or not a solution exists for allocating the programmable memory for the desired features given the plurality of constraints; and returning the result. ### Claim 2 (depends on 1) The method of claim 1, wherein the result indicates that the solution exists for allocating the programmable memory for the desired features given the plurality of constraints, and wherein the result comprises a memory profile of an allocation of the programmable memory for the desired features. ### Claim 3 (depends on 1) The method of claim 1, further comprising: wherein the result indicates that no solution exists for allocating the programmable memory for the desired features given the plurality of constraints, wherein the result comprises a notification that indicates an allocation of the programmable memory is not feasible, and wherein the notification comprises at least one reason for the allocation not being feasible. ### Claim 4 (depends on 1) The method of claim 1, wherein the features comprise at least one of the following: Layer 2 switching and Layer 3 routing. ### Claim 5 (depends on 1) The method of claim 1, wherein the plurality of constraints comprises scale constraints, connectivity constraints, and hardware constraints. ### Claim 6 (depends on 5) The method of claim 5, wherein the hardware constraints comprise: a number of a first type of memory groups with a first row size; and a number of a second type of memory groups with a second row size. ### Claim 7 (depends on 1) The method of claim 1, wherein the programmable memory in the network device is an application-specific integrated circuit (ASIC) memory. ### Claim 8 (depends on 1) The method of claim 1, wherein the set of desired features for the network device is selected by a user. ### Claim 9 A non-transitory computer readable medium comprising computer readable program code, which when executed by a computer processor enables the computer processor to perform a method, the method comprising: receiving a set of desired features for a network device, wherein the set of desired features comprises a Layer 2 switching feature or a Layer 3 routing feature and wherein the given Layer 2 switching feature is supported by at least a Layer 2 address database to be stored across multiple memory groups of programmable memory of the network device; determining a plurality of constraints associated with the set of desired features, wherein the plurality of constraints comprises a number of banks to be used in each of the multiple memory groups for the Layer 2 address database and wherein the plurality of constraints comprises a scale requirement associated with a memory allocation in some of the multiple memory groups that is reserved for a scaling of the Layer 2 address database; and evaluating a feasibility of allocating the programmable memory for the desired features based on the plurality of constraints at least in part by evaluating a feasibility of allocating portions of the multiple memory groups to the Layer 2 address database based on the number of banks to be used in each of the multiple memory groups and based on the scale requirement. ### Claim 10 (depends on 9) The non-transitory computer readable medium of claim 9, the method further comprising: converting the plurality of constraints into a plurality of Boolean representations of the constraints; and wherein the evaluation of the feasibility of allocating the programmable memory is based on the plurality of representations of the constraints. ### Claim 11 (depends on 9) The non-transitory computer readable medium of claim 9, the method further comprising: determining that the allocation of the programmable memory is feasible; and generating, in response to the determination that the allocation of the programmable memory is feasible, the allocation of the programmable memory for the desired features. ### Claim 12 (depends on 9) The non-transitory computer readable medium of claim 9, the method further comprising: determining that the allocation of the programmable memory is not feasible; and generating, based on the determination that the allocation of the programmable memory is not feasible, at least one reason for the allocation of the programmable memory not being feasible based on the evaluation of the feasibility of allocating the programmable memory. ### Claim 13 (depends on 9) The non-transitory computer readable medium of claim 9, wherein the plurality of constraints comprises connectivity constraints and hardware constraints. ### Claim 14 (depends on 13) The non-transitory computer readable medium of claim 13, wherein the hardware constraints comprise: a number of a first type of memory groups with a first row size; and a number of a second type of memory groups with a second row size. ### Claim 15 (depends on 9) The non-transitory computer readable medium of claim 9, wherein the evaluation of the feasibility of allocating the programmable memory is performed using a Satisfiability Modulo Theories (SMT) solver. ### Claim 16 (depends on 9) The non-transitory computer readable medium of claim 9, wherein the set of desired features for the network device is selected by a user. ### Claim 17 A network device comprising: a processor and a memory, wherein the processor and memory are configured to: receive a set of desired features for the network device, wherein each feature in the set of desired features is supported by a data structure to be implemented on memory blocks of programmable memory; determine a plurality of constraints associated with the set of desired features, wherein the plurality of constraints comprises connectivity constraints for the data structures supporting the set of desired features and wherein the connectivity constraints for the data structures each indicate one or more connections to at least a subset of the memory blocks of the programmable memory; evaluate a feasibility of allocating the memory blocks of the programmable memory for the desired features based at least in part on the connectivity constraints; and issue a notification that allocating the memory blocks of the programmable memory for the desired features is infeasible, wherein the notification comprises a conflict in memory allocation between first and second features in the set of desired features that is identified by the feasibility evaluation. ### Claim 18 (depends on 17) The network device of claim 17, wherein the processor and memory are further configured to: convert the plurality of constraints into a plurality of Boolean representations of the constraints; and wherein the evaluation of the feasibility is based on the plurality of representations of the constraints. ### Claim 19 (depends on 17) The network device of claim 17, wherein the plurality of constraints comprises first additional constraints indicating a number of memory blocks usable to implement each of the data structures and second additional constraints indicating contiguity of memory block allocation for each feature in the set of desired features and wherein the feasibility of allocating the memory blocks of the programmable memory for the desired features is evaluated based at least in part on the first and second additional constraints.