# US 12,113,615 B2 · CRC bits for joint decoding and verification of control information using polar codes

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- Number: US 12,113,615 B2
- Document ID: US12113615B2
- Status: Granted
- Kind: B2
- Application number: 18/332,412
- Filed: 2023-06-09
- Published: 2023-10-19
- Granted: 2024-10-08
- Earliest claimed: 2016-12-15
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Changlong Xu; Joseph Binamira Soriaga; Jilei Hou
- Web page: https://patentgrep.com/patent/US12113615B2

## CPC

- H03M 13/13: Linear codes
- H04L 1/0061: {Error detection codes}
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)}
- H04L 43/0847: {Transmission error}
- H04L 69/324: in the data link layer [OSI layer 2], e.g. HDLC
- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Aspects of the disclosure relate to wireless communication systems configured to provide techniques for polar coding control information together with combined cyclic redundancy check (CRC) information. The combined CRC information may include a number of CRC bits selected to jointly decode and verify the control information to reduce the CRC overhead.

## Claims

### Claim 1

A method of wireless communication, comprising:
generating cyclic redundancy check (CRC) information for an information block, wherein the information block comprises control information, wherein the CRC information comprises at least a total number of combined CRC bits equal to a sum of a first number of integrity check bits and a second number of CRC-aided successive-cancellation list (SCL) bits;
encoding the information block, including the CRC information, utilizing polar coding to generate a polar code block; and
providing the polar code block over a wireless air interface.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
selecting the second number of the CRC-aided SCL bits is selected based on a list size associated with successive cancellation list (SCL) decoding.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
selecting the second number of the CRC-aided SCL bits to be equal to a binary logarithm of the list size.

### Claim 4 (depends on 3)

The method of claim 3, wherein:
the second number of the CRC-aided SCL bits comprises three bits when the list size is equal to eight; and
the second number of the CRC-aided SCL bits comprises five bits when the list size is equal to thirty-two.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first number of the integrity check bits comprises sixteen bits.

### Claim 6 (depends on 1)

The method of claim 1, wherein the information block comprises a plurality of original bit locations and the polar code block comprises a plurality of coded bit locations, wherein each of the plurality of coded bit locations corresponds to one of a plurality of sub-channels, and wherein generating the information block further comprises:
determining a reliability metric for each of the original bit locations to produce a plurality of reliability metrics;
sorting the plurality of sub-channels based on the plurality of reliability metrics in order from highest reliability metrics to lowest reliability metrics; and
allocating a portion of the plurality of sub-channels either comprising the highest reliability metrics or distributed among the plurality of sub-channels to the CRC information.

### Claim 7 (depends on 1)

The method of claim 1, wherein generating the CRC information further comprises:
adding an additional number of zero bits to the control information to produce a first polynomial, wherein the additional number of the zero bits is equal to the total number of the combined CRC bits;
dividing the first polynomial by a generator polynomial to produce a remainder polynomial comprising the total number of the combined CRC bits;
scrambling the combined CRC bits with an identifier associated with a scheduled entity to receive the polar code block to produce the CRC information; and
appending the CRC information to the control information in the information block.

### Claim 8

An apparatus configured for polar coding, the apparatus comprising:
one or more processors; and
one or more memories coupled to the one or more processors,
wherein the one or more processors are configured to:
generate cyclic redundancy check (CRC) information for an information block, wherein the information block comprises control information, wherein the CRC information comprises at least a total number of combined CRC bits equal to a sum of a first number of integrity check bits and a second number of CRC-aided successive-cancellation list (SCL) bits;
encode the information block, including the CRC information, utilizing polar coding to generate a polar code block; and
provide the polar code block over a wireless air interface.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the one or more processors are further configured to:
select the second number of the CRC-aided SCL bits based on a list size associated with successive cancellation list (SCL) decoding.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the one or more processors are further configured to:
select the second number of the CRC-aided SCL bits to be equal to a binary logarithm of the list size.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein:
the second number of the CRC-aided SCL bits comprises three bits when the list size is equal to eight; and
the second number of the CRC-aided SCL bits comprises five bits when the list size is equal to thirty-two.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the first number of the integrity check bits comprises sixteen bits.

### Claim 13 (depends on 8)

The apparatus of claim 8, wherein the information block comprises a plurality of original bit locations and the polar code block comprises a plurality of coded bit locations, wherein each of the plurality of coded bit locations corresponds to one of a plurality of sub-channels, and wherein the one or more processors are further configured to:
determine a reliability metric for each of the original bit locations to produce a plurality of reliability metrics;
sort the plurality of sub-channels based on the plurality of reliability metrics in order from highest reliability metrics to lowest reliability metrics; and
allocate a portion of the plurality of sub-channels either comprising the highest reliability metrics or distributed among the plurality of sub-channels to the CRC information.

### Claim 14 (depends on 8)

The apparatus of claim 8, wherein the one or more processors are further configured to:
add an additional number of zero bits to the control information to produce a first polynomial, wherein the additional number of the zero bits is equal to the number of the combined CRC bits;
divide the first polynomial by a generator polynomial to produce a remainder polynomial comprising the number of the combined CRC bits;
scramble the combined CRC bits with an identifier associated with a scheduled entity to receive the polar code block to produce the CRC information; and
append the CRC information to the control information in the information block.

### Claim 15

A method of wireless communication operable at a user equipment (UE), comprising:
receiving a polar code block comprising control information for the UE and cyclic redundancy check (CRC) information comprising at least a total number of combined CRC bits equal to a sum of a first number of integrity check bits and a second number of CRC-aided successive-cancellation list (SCL) bits;
decoding the polar code block utilizing SCL decoding and the CRC information to produce an information block comprising the control information and the CRC information; and
verifying an integrity of the control information utilizing the CRC information.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second number of CRC-aided SCL bits is selected based on a list size utilized in the SCL decoding.

### Claim 17 (depends on 16)

The method of claim 16, wherein the second number of CRC-aided SCL bits is equal to a binary logarithm of the list size.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
the second number of the CRC-aided SCL bits comprises three bits when the list size is equal to eight; and
the second number of the CRC-aided SCL bits comprises five bits when the list size is equal to thirty-two.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first number of the integrity check bits comprises sixteen bits.

### Claim 20 (depends on 15)

The method of claim 15, wherein the information block comprises a plurality of original bit locations and the polar code block comprises a plurality of coded bit locations, wherein each of the coded bit locations corresponds to one of a plurality of sub-channels, and wherein receiving the polar code block further comprises:
receiving the CRC information within a portion of the plurality of sub-channels either comprising highest reliability metrics or distributed among the plurality of sub-channels.

### Claim 21 (depends on 15)

The method of claim 15, wherein verifying the integrity of the control information utilizing the CRC information further comprises:
descrambling the CRC information utilizing an identifier associated with the UE to produce the combined CRC bits;
dividing the information block comprising the control information and the combined CRC bits by a generator polynomial to produce a remainder; and
if the remainder is equal to zero, verifying the control information is correctly received.

### Claim 22 (depends on 15)

The method of claim 15, wherein decoding the polar code block utilizing SCL decoding and the CRC information further comprises:
decoding the polar code block to produce a plurality of information block candidates, wherein a number of the plurality of information block candidates is equal to a list size utilized in the SCL decoding; and
utilizing the CRC information to select one of the plurality of information block candidates as the information block.

### Claim 23

An apparatus configured for polar decoding, the apparatus comprising:
one or more processors; and
one or more memories coupled to the one or more processors,
wherein the one or more processors are configured to:
receive a polar code block comprising control information and cyclic redundancy check (CRC) information comprising at least a total number of combined CRC bits equal to a sum of a first number of integrity check bits and a second number of CRC-aided successive-cancellation list (SCL) bits;
decode the polar code block utilizing SCL decoding and the CRC information to produce an information block comprising the control information and the CRC information; and
verify an integrity of the control information utilizing the CRC information.

### Claim 24 (depends on 23)

The apparatus of claim 23, wherein the second number of CRC-aided SCL bits is selected based on a list size utilized in the SCL decoding.

### Claim 25 (depends on 24)

The apparatus of claim 24, wherein the second number of CRC-aided SCL bits is equal to a binary logarithm of the list size.

### Claim 26 (depends on 25)

The apparatus of claim 25, wherein:
the second number of the CRC-aided SCL bits comprises three bits when the list size is equal to eight; and
the second number of the CRC-aided SCL bits comprises five bits when the list size is equal to thirty-two.

### Claim 27 (depends on 26)

The apparatus of claim 26, wherein the first number of the integrity check bits comprises sixteen bits.

### Claim 28 (depends on 23)

The apparatus of claim 23, wherein the information block comprises a plurality of original bit locations and the polar code block comprises a plurality of coded bit locations, wherein each of the coded bit locations corresponds to one of a plurality of sub-channels, and wherein the one or more processors are further configured to:
receive the CRC information within a portion of the plurality of sub-channels either comprising highest reliability metrics or distributed among the plurality of sub-channels.

### Claim 29 (depends on 23)

The apparatus of claim 23, wherein the one or more processors are further configured to:
descramble the CRC information utilizing an identifier associated with the apparatus to produce the combined CRC bits;
divide the information block comprising the control information and the combined CRC bits by a generator polynomial to produce a remainder; and
if the remainder is equal to zero, verify the control information is correctly received.

### Claim 30 (depends on 23)

The apparatus of claim 23, wherein the one or more processors are further configured to:
decode the polar code block to produce a plurality of information block candidates, wherein a number of the plurality of information block candidates is equal to a list size utilized in the SCL decoding; and
utilize the CRC information to select one of the plurality of information block candidates as the information block.