# US 12,113,575 B2 · 10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,113,575 B2
- Document ID: US12113575B2
- Status: Granted
- Kind: B2
- Application number: 18/324,792
- Filed: 2023-05-26
- Published: 2023-11-30
- Granted: 2024-10-08
- Earliest claimed: 2022-05-26
- Applicants: Xiamen Eochip Semiconductor Co., Ltd
- Inventors: Jinghu Li; Zhang Fan; An Lin
- Web page: https://patentgrep.com/patent/US12113575B2

## CPC

- H04B 10/503: {Laser transmitters}
- H04B 10/272: Star-type networks {or tree-type networks}
- H04B 10/40: Transceivers
- H04B 10/564: Power control
- H04B 10/69: Electrical arrangements in the receiver
- H04Q 11/0067: {Provisions for optical access or distribution networks, e.g. Gigabit Ethernet Passive Optical Network (GE-PON), ATM-based Passive Optical Network (A-PON), PON-Ring}
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- Y02D 30/70: in wireless communication networks
- H04B: TRANSMISSION
- H04Q: SELECTING (switches, relays, selectors H01H; wireless communication networks H04W)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A 10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser includes: a burst mode receiver RX which processes amplitude detection, and outputs the signal whose amplitude and waveform pulse width met the threshold requirements to a host, and comprises a fast recovery module to discharge charges in an AC coupling capacitor to achieve multi-packet transmission without mutual interference and to meet the timing sequence requirement of the XGSPON protocol; a continuous mode transmitter TX which receives the electrical signal attenuated by a PCB board, and selects a bypass BYPASS path or a clock data recovery CDR path according to a degree of attenuation to drive the EML laser; a digital control unit DIGIITAL which communicates with the host and provides control signals to the burst mode receiver RX and the continuous mode transmitter TX; and a power module POWER.

## Claims

### Claim 1

A 10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser, comprising:
a burst mode receiver RX, a continuous mode transmitter TX and a digital control unit DIGIITAL, and a power module POWER;
wherein the burst mode receiver RX amplifies an electrical signal which is originated from an optical signal from each ONU client and processed through a burst mode receiver TIA, processes amplitude detection of the electrical signal, determines if the electrical signal has an amplitude meeting threshold requirements, and output a detection result to a host, and uses a fast recovery module to discharge charges in an AC coupling capacitor to achieve multi-packet transmission without mutual interference, thereby meeting a XGSPON protocol;
the continuous mode transmitter TX receives the electrical signal attenuated by a PCB board, and in response to a degree of attenuation, selects a bypass path BYPASS for transmission or outputs the electrical signal after a signal quality of the electrical signal is processed and improved by a clock data recovery path CDR to drive the EML laser;
the digital control unit DIGIITAL communicates with the host, and provides control signals to the burst mode receiver RX and the continuous mode transmitter TX; and
the power module POWER is arranged to provide power supply to the chip;
the burst mode receiver RX comprises pre-amplifier Pre_Amplifier, a level detector Level Dectector, a 10G burst-mode limiting amplifier BurstLA_10G, a current mode logic output buffer CML BUFFER, a signal detection output buffer BUFFER and a fast recovery module;
a non-inverting input and an inverting input of the pre-amplifier Pre_Amplifier are arranged to receive a burst data packet (the electrical signal) from the burst transimpedance amplifier TIA; the fast very module is arranged to provide a fast recovery circuit to ensure a timing sequence is correct, so that physical collision of two adjacently time sequenced burst packets is avoided;
an output terminal of the pre-amplifier Pre_Amplifier is simultaneously connected to an input terminal of the 10G burst-mode limiting amplifier BurstLA_10G and an input terminal of the level detector LEVEL DETECTOR;
an output terminal of the 10G burst-mode limiting amplifier BurstLA_10G Is connected to an input terminal of the current mode logic buffer CML BUFFER;
an output terminal of the level detector LEVEL DETECTOR is simultaneously connected to input terminal of the signal detection output buffer BUFFER and an on/off control terminal of the current mode logic output buffer CML BUFFER;
two output terminals of the current mode logic output buffer CML Buffer are connected to output pins RX_OUTP and RX_OUTN of the burst mode receiver RX respectively;
an output terminal of the signal detection output buffer BUFFER is connected to a chip pin RX_SD, and the burst mode receiver RX sends a detection result to the host through the chip pin RX_SD;
wherein in response to a reset signal sent from the host and received by a chip pin LA_RESET, the chip sends a feedback signal to the host through the pin RX_SD;
the fast recovery module is built-in or external to the burst mode receiver RX, and the fast recovery module comprises resistors R7, R8, R9, R10, and switches S1 and S2,
when the fast recovery module is external to the burst mode receiver RX, a non-inverting output terminal of the burst transimpedance amplifier TIA is connected to one end of the resistor R10 of the fast recover module, one end of the resistor R8 of the fast recovery module and a non-inverting input pin RX_INP of the chip through an AC coupling capacitor C9;
an inverting output terminal of the burst transimpedance amplifier TIA is connected to one end of the resistor R9 and one end of the resistor R7 of the fast recovery module, and an inverting input pin RX_INN of the chip through the AC coupling capacitor C8;
a non-inverting input pin RX_INP of the chip and an inverting input pin RX_INN of the chip are connected to a non-inverting input terminal and an inverting input terminal of the pre-amplifier Pre_Amplifier respectively;
another end of the resistor R10 is connected to one end of the switch S1;
another end of the resistor R9 is connected to one end of the switch S2;
control ends of the switches S1 and S2 are connected to a reset signal line LA_RESET simultaneously; and
a reference voltage pin Vref of the burst mode receiver RX is simultaneously connected to another end of the resistor R7, another end of the R8, another end of the switch S1 and another end of the switch S2,
when the fast recovery module is built in the burst mode receiver RX, a non-inverting output terminal and an inverting output terminal of the burst transimpedance amplifier TIA are connected to a non-inventing input pin RX_INP of the chip and an inverting input pin RX_INN of the chip through AC coupling capacitors C9 and C8,
inside the chip, the non-inverting input pin RX_INP of the chip is connected to one end of the resistor R10, one end of the resistor R8 and a non-inverting input terminal of the pre-amplifier Pre_Amplifier;
the inventing input pin RX_INN of the chip is connected to one end of the resistor R9, one end of the resistor R7 and an inverting input of the pre-amplifier Pre_Amplifier;
another end of the resistor R10 is connected to one end of the switch S1;
another end of the resistor R9 is connected to one end of the switch S2;
control ends of the switches S1 and S2 are connected to a reset signal line LA_RESET of the chip simultaneously, and
a reference voltage Vref of the burst mode receiver RX is simultaneously connected to another end of the resistor R7, another end of the R8, another end of the switch S1 and another end of the switch S2.

### Claim 2 (depends on 1)

The 10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser according to claim 1, wherein the continuous mode transmitter TX comprises an input buffer INPUT BUFFER, the bypass ByPass, the clock data recovery CDR, a EML laser driver, and a bias current control unit,
wherein one of the bypass ByPass path or the clock data recovery CDR path is selected to activate,
an attenuated signal formed by an original high-speed electrical signal (the burst data packet) passing through a metal trace on a PCB board is connected to the input buffer INPUT BUFFER through the chip pins TX_INP and TX_INN, then the input buffer INPUT BUFFER transmits the attenuated signal to the input terminal of the EML laser driver along the activated path; an output terminal of the EML laser driver is connected to a control terminal of the EML laser through chip pin TX_OUTP;
a bias current output terminal of the bias current control unit is connected to the chip pin BIAS, and provides a bias current for the EML laser;
the host sends commands to the chip to turn off the bias current through the chip pin TXDIS to turn off the continuous mode transmitter TX.

### Claim 3 (depends on 2)

The 10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser according to claim 2, wherein the activation of one of the bypass ByPass or the clock data recovery CDR path is controlled by digital control unit DIGITAL according to an external command.

### Claim 4 (depends on 2)

The 10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser according to claim 2, wherein the activation of one of the bypass ByPass path or the clock data recovery CDR path is controlled by the host switching a path automatically by itself, if a detected rate of the original high-speed electrical signal is below 8G, the signal attenuation is not serious, and the bypass ByPass path is activated; if the detected rate of the original high-speed electrical signal is 8G-14G, the signal attenuation is serious, and the clock data recovery CDR path is activated by the host.

### Claim 5 (depends on 1)

The 10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser according to claim 1, the digital control unit DIGITAL comprises a register digital core, an analog-to-digital converter ADC, a I2C slave and temperature sensor TEMP SENSOR;
an output terminal of the temperature sensor TEMP SENSOR is connected to a temperature signal input terminal of the register digital core through the analog-to-digital converter ADC;
an input terminal of I2C slave is connected to a pin SCL of a clock chip; an input and output ports of I2C slave are connected to a pin SDA of an external command chip; an output terminal of I2C slave is connected to an external command input terminal of the register digital core, and the register digital core controls a path activation of the continuous mode transmitter TX; the register digital core also realizes a configuration of the burst mode receiver RX and the continuous mode transmitter TX through a control port.

### Claim 6 (depends on 5)

The 10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser according to claim 5, wherein the control port for configuring the burst mode receiver RX in the digital control unit Digital comprises an eye cross point adjustment control port CPA, an output swing control port SW CTRL, an output polarity inversion control port POL CTRL, and a signal loss control port LOS CTRL;
wherein the control port for configuring the continuous mode transmitter TX in the digital control unit Digital comprises an optical power control port APC, an eye cross point adjustment control port CPA, a jitter optimization control port EQ, an eye diagram optimization control port EO and an output polarity inversion control port POL CTRL; and
an input terminal of the optical power control port APC is connected to a chip pin MPD for monitoring current.

### Claim 7 (depends on 1)

The 10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser according to claim 1, wherein the power module POWER comprises a DC power supply VDC, a DC chopper DC/DC, and resistors R1 and R2;
wherein the DC power supply VDC provides working power for the EML laser driver while the DC chopper DC/DC converts the DC power VDC into a DC power VCC1 and outputs it through the pin VOUT; the DC power supply VCC1 provides the working power for the burst mode receiver RX, the continuous mode transmitter TX and the digital control unit Digital respectively;
the output terminal VOUT of the DC chopper DC/DC is connected to one end of the resistor R1 and a chip pin CAP1 simultaneously; the chip pin CAP1 is grounded through a capacitor C2;
another end of the resistor R1 is simultaneously connected to one end of the resistor R2 and a feedback signal terminal FB of the DC chopper DC/DC;
another end of the resistor R2 is grounded;
a switch input port SW of the DC chopper DC/DC is connected to a chip pin SW1; the chip pin SW1 is connected to a positive terminal of the DC power supply VDC through an inductor L1;
a power supply voltage port VCC of the DC chopper DC/DC is connected to a chip pin VDC; the chip pin VDC is connected to the positive terminal of the DC power supply VDC; and
an enable port EN of the DC chopper DC/DC is connected to a chip pin EN1; the chip pin EN1 is connected to one end of a capacitor C1 and the positive terminal of the DC power supply VDC at the same time; another end of the capacitor C1 is grounded, and a negative terminal of the DC power supply VDC is grounded.

### Claim 8 (depends on 1)

The 10G rate OLT terminal transceiver integrated chip based on XGSPON with EML laser according to claim 1, wherein the power module POWER comprises a DC power supply VDC, a DC power supply VCC, a first DC chopper DC/DC, a second DC chopper DC/DC, and resistors R1-R4;
wherein the first DC chopper DC/DC converts the DC power supply VDC into a DC power supply VCC1 and outputs it through a pin VOUT; the DC power supply VCC1 provides working power for the burst mode receiver RX, the continuous mode transmitter TX and the digital control unit Digital respectively;
an output terminal VOUT of the first DC chopper DC/DC is connected to one end of the resistor R1 and a chip pin CAP1 simultaneously; the chip pin CAP1 is grounded through a capacitor C2;
another end of the resistor R1 is simultaneously connected to one end of the resistor R2 and a feedback signal terminal FB of the first DC chopper DC/DC;
another end of the resistor R2 is grounded;
a switch input port SW of the first DC chopper DC/DC is connected to a chip pin SW1; the chip pin SW1 is connected to a positive terminal of the DC power supply VDC through an inductor L1;
a power supply voltage port VCC of the first DC chopper DC/DC is connected to a chip pin VDC; the chip pin VDC is connected to the positive terminal of the DC power supply VDC;
an enable port EN of the first DC chopper DC/DC is connected to a chip pin EN1; the chip pin EN1 is connected to one end of a capacitor C1 and the positive terminal of the DC power supply VDC at the same time; another end of the capacitor C1 is grounded, and a negative terminal of the DC power supply VDC is grounded;
the second DC chopper DC/DC converts the DC power supply VCC into a DC power supply VCC2 and outputs it through a pin VOUT; the DC power supply VCC2 provides working power for the EML laser driver;
the output terminal VOUT of the second DC chopper DC/DC is connected to one end of the resistor R3 and a chip pin CAP2 simultaneously; the chip pin CAP2 is grounded through a capacitor C4;
another end of the resistor R3 is simultaneously connected to one end of the resistor R4 and a feedback signal terminal FB of the second DC chopper DC/DC;
another end of the resistor R4 is grounded;
a switch input port SW of the second DC chopper DC/DC is connected to a chip pin SW2; the chip pin SW2 is connected to a positive terminal of the DC power supply VCC through an inductor L2;
a power supply voltage port VCC of the second DC chopper DC/DC is connected to a chip pin VCC; the chip pin VCC is connected to the positive terminal of the DC power supply VCC;
an enable port EN of the second DC chopper DC/DC is connected to a chip pin EN2; the chip pin EN2 is connected to one end of a capacitor C3 and the positive terminal of the DC power supply VCC at the same time; another end of the capacitor C3 is grounded, and a negative terminal of the DC power supply VCC is grounded.