# US 12,113,551 B2 · Calibration of anti-aliasing filter mismatch

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- Number: US 12,113,551 B2
- Document ID: US12113551B2
- Status: Granted
- Kind: B2
- Application number: 17/895,897
- Filed: 2022-08-25
- Published: 2024-02-29
- Granted: 2024-10-08
- Earliest claimed: 2022-08-25
- Assignees: Cirrus Logic, Inc.
- Applicants: Cirrus Logic International Semiconductor Ltd.
- Inventors: Arashk Norouzpourshirazi; John L. Melanson; Axel Thomsen
- Web page: https://patentgrep.com/patent/US12113551B2

## CPC

- H03M 3/38: {Calibration}
- H03M 3/344: {by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing}
- H03M 3/458: {Analogue/digital converters using delta-sigma modulation as an intermediate step}
- H03F 3/217: Class D power amplifiers; Switching amplifiers
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03F: AMPLIFIERS

## Abstract

In accordance with embodiments of the present disclosure, a method may include, in a system comprising a differential filter comprising a plurality of impedance elements, applying a common-mode signal to the differential filter, measuring an output signal of the differential filter in response to the common-mode signal to determine an error due to impedance mismatch of the impedance elements, and tuning one or more of the plurality of impedance elements to minimize the error.

## Claims

### Claim 1

A method comprising, in a system comprising a differential filter comprising a plurality of impedance elements:
applying a common-mode signal to the differential filter;
measuring an output signal of the differential filter in response to the common-mode signal to determine an error due to impedance mismatch of the impedance elements; and
tuning one or more of the plurality of impedance elements to minimize the error.

### Claim 2 (depends on 1)

The method of claim 1, wherein applying the common-mode signal to the differential filter comprises applying the common-mode signal to inputs of the differential filter.

### Claim 3 (depends on 1)

The method of claim 1, wherein applying the common-mode signal to the differential filter comprises applying the common-mode signal to common-mode ground nodes of capacitors of the differential filter.

### Claim 4 (depends on 1)

The method of claim 1, wherein tuning one or more of the plurality of impedance elements comprises tuning one or more capacitances of the differential filter.

### Claim 5 (depends on 1)

The method of claim 1, wherein tuning one or more of the plurality of impedance elements comprises tuning one or more resistances of the differential filter.

### Claim 6 (depends on 1)

The method of claim 1, wherein the common-mode signal is greater than one-half of a sampling frequency of an analog-to-digital converter that receives the output signal of the differential filter.

### Claim 7 (depends on 1)

The method of claim 1, wherein tuning comprises using a closed-loop controller to tune the one or more of the plurality of impedance elements responsive to the error.

### Claim 8 (depends on 1)

The method of claim 1, wherein measuring an output of the differential filter comprises:
converting the output signal to a digital equivalent signal; and
tuning one or more of the plurality of impedance elements to minimize the digital equivalent signal.

### Claim 9

A system comprising:
a signal generator configured to apply a common-mode signal to a differential filter comprising a plurality of impedance elements;
an error extractor configured to measure an output signal of the differential filter in response to the common-mode signal to determine an error due to impedance mismatch of the impedance elements; and
a controller configured to tune one or more of the plurality of impedance elements to minimize the error.

### Claim 10 (depends on 9)

The system of claim 9, wherein applying the common-mode signal to the differential filter comprises applying the common-mode signal to inputs of the differential filter.

### Claim 11 (depends on 9)

The system of claim 9, wherein applying the common-mode signal to the differential filter comprises applying the common-mode signal to common-mode ground nodes of capacitors of the differential filter.

### Claim 12 (depends on 9)

The system of claim 9, wherein tuning one or more of the plurality of impedance elements comprises tuning one or more capacitances of the differential filter.

### Claim 13 (depends on 9)

The system of claim 9, wherein tuning one or more of the plurality of impedance elements comprises tuning one or more resistances of the differential filter.

### Claim 14 (depends on 9)

The system of claim 9, wherein the common-mode signal is greater than one-half of a sampling frequency of an analog-to-digital converter that receives the output signal of the differential filter.

### Claim 15 (depends on 9)

The system of claim 9, wherein tuning comprises using a closed-loop controller to tune the one or more of the plurality of impedance elements responsive to the error.

### Claim 16 (depends on 9)

The system of claim 9, wherein measuring an output of the differential filter comprises:
converting the output signal to a digital equivalent signal; and
tuning one or more of the plurality of impedance elements to minimize the digital equivalent signal.