Application of low-density parity-check codes with codeword segmentation
AssigneeIntel Corporation
InventorsSanthosh K. Vanaparthy, Ravi H. Motwani
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Abstract
A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.
Claims20
A low-density parity-check (LDPC) decoder circuit, comprising:
- a segment calculator circuit to segment a codeword of length C bits into N non-overlapping segments of C/N bits, where N is an integer greater than one, and compute an expected error rate for the N non-overlapping segments;
- and
- an error correction code (ECC) computation circuit having check nodes, the ECC computation circuit to perform check node computations, including to first perform decode computations for the N non-overlapping segments, on separate C/N bits at a time with the check nodes, including to adjust the decode computations based on the expected error rate for selected segments of the codeword, and then to perform decode computations for the C bits of the codeword together, based on the decode computations for the N non-overlapping segments.
A method for decoding, comprising:
- segmenting a codeword of length C bits into N non-overlapping segments of C/N bits with a low-density parity-check (LDPC) decoder circuit, where N is an integer greater than one;
- performing check node computations with the LDPC decoder circuit, including first performing decode computations for the N non-overlapping segments of C/N bits, including adjusting the decode computations based on an expected error rate for selected segments of the codeword;
- and then,
- performing decode computations with the LDPC decoder circuit for the C bits of the codeword together, based on the decode computations for the N non-overlapping segments.
An apparatus comprising a computer readable storage medium having content stored thereon, which when executed causes a machine having a low-density parity-check (LDPC) decoder circuit to perform a method for decoding including:
- segmenting a codeword of length C bits into N non-overlapping segments of C/N bits with the LDPC decoder circuit, where N is an integer greater than one;
- performing check node computations as (N+1) segments of check nodes with the LDPC decoder circuit, including first performing decode computations for the N non-overlapping segments with N segments of the check nodes, including adjusting the decode computations based on an expected error rate for selected segments of the codeword;
- and then,
- performing decode computations for the C bits of the codeword with the LDPC decoder circuit, based on the decode computations for the N non-overlapping segments.
Dependencies are inferred from the claim text.