# US 12,113,545 B2 · Capacitor digital-to-analog converter using random reset signal and integrated circuit including the same

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- Number: US 12,113,545 B2
- Document ID: US12113545B2
- Status: Granted
- Kind: B2
- Application number: 17/872,173
- Filed: 2022-07-25
- Published: 2023-04-27
- Granted: 2024-10-08
- Earliest claimed: 2021-10-22
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yanghoon Lee; Wan Kim
- Web page: https://patentgrep.com/patent/US12113545B2

## CPC

- H03M 1/0656: {in the time domain, e.g. using intended jitter as a dither signal}
- H03M 1/802: {using capacitors, e.g. neuron-mos transistors, charge coupled devices}
- H03M 1/0863: {of switching transients, e.g. glitches}
- H03M 1/68: with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
- H03M 1/804: {with charge redistribution}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A capacitor digital-to-analog converter (CDAC) includes a clock generator, a random reset control signal generator, a first capacitor array, a first reset circuit and an output buffer. The clock generator generates an internal clock signal and a reset control signal that are regularly toggled. The random reset control signal generator generates a random reset control signal that is irregularly toggled. The first capacitor array includes a plurality of capacitors connected to a first summation node, and generates a first summation voltage corresponding to a first input digital signal based on first and second reference voltages. The first reset circuit initializes the first summation node based on the random reset control signal. The output buffer generates a first analog output voltage by buffering the first summation voltage.

## Claims

### Claim 1

A capacitor digital-to-analog converter (CDAC) comprising:
a clock generator configured to generate an internal clock signal and a reset control signal based on an external clock signal, the internal clock signal being regularly toggled, the reset control signal being regularly toggled;
a random reset control signal generator configured to generate a random reset control signal based on the reset control signal, the random reset control signal being irregularly toggled;
a first capacitor array including a plurality of capacitors, and configured to generate a first summation voltage based on a first reference voltage and a second reference voltage, the plurality of capacitors in the first capacitor array being connected to a first summation node and having different capacitances, the first summation voltage corresponding to a first input digital signal;
a first reset circuit configured to initialize the first summation node based on the random reset control signal and a change in the first input digital signal; and
an output buffer configured to generate a first analog output voltage by buffering the first summation voltage,
wherein the capacitor digital-to-analog converter is configured to operate in a reset phase for initializing the first summation node, and during the reset phase, a value of the first input digital signal sequentially increases based on the internal clock signal.

### Claim 2 (depends on 1)

The capacitor digital-to-analog converter of claim 1, wherein the random reset control signal generator includes:
a pseudorandom number generator configured to generate a pseudorandom number signal based on the internal clock signal; and
a logic circuit configured to generate the random reset control signal based on the pseudorandom number signal and the reset control signal.

### Claim 3 (depends on 2)

The capacitor digital-to-analog converter of claim 2, wherein the logic circuit includes:
an AND gate configured to perform an AND operation on the pseudorandom number signal and the reset control signal.

### Claim 4 (depends on 1)

The capacitor digital-to-analog converter of claim 1, wherein the first reset circuit includes:
a first switch connected between a reset voltage and the first summation node, and configured to be turned on and off based on the random reset control signal.

### Claim 5 (depends on 1)

The capacitor digital-to-analog converter of claim 1, wherein:
the capacitor digital-to-analog converter is configured to operate in a conversion phase subsequent to the reset phase,
during the reset phase, the reset control signal is regularly toggled, and the random reset control signal is irregularly toggled, and
during the conversion phase, the reset control signal and the random reset control signal have a deactivation state.

### Claim 6 (depends on 5)

The capacitor digital-to-analog converter of claim 5, wherein:
during a unit interval in the reset phase, a sum of lengths of first activation periods in which the reset control signal has an activation state and a sum of lengths of first deactivation periods in which the reset control signal has the deactivation state are equal to each other, and
during the unit interval in the reset phase, a sum of lengths of second activation periods in which the random reset control signal has the activation state and a sum of lengths of second deactivation periods in which the random reset control signal has the deactivation state are different from each other.

### Claim 7 (depends on 6)

The capacitor digital-to-analog converter of claim 6, wherein:
during the second activation periods in the reset phase, a voltage level of the first summation voltage at the first summation node is initialized to a voltage level of a reset voltage, and
during the second deactivation periods in the reset phase, the voltage level of the first summation voltage at the first summation node sequentially increases based on the first input digital signal.

### Claim 8 (depends on 6)

The capacitor digital-to-analog converter of claim 6, wherein, during the conversion phase, the first input digital signal has a target value for a digital-to-analog conversion, and the first summation voltage has a target voltage level corresponding to the target value.

### Claim 9 (depends on 1)

The capacitor digital-to-analog converter of claim 1, wherein:
the plurality of capacitors in the first capacitor array include first to N-th capacitors, where N is a natural number greater than or equal to two, and
a capacitance of the N-th capacitor is 2(N−1) times a capacitance of the first capacitor.

### Claim 10 (depends on 9)

The capacitor digital-to-analog converter of claim 9, wherein the first capacitor array further includes:
first to N-th switches connected to the first to N-th capacitors, and configured to provide one of the first reference voltage and the second reference voltage to the first to N-th capacitors based on bits of the first input digital signal.

### Claim 11 (depends on 1)

The capacitor digital-to-analog converter of claim 1, further comprising:
a reference voltage generator configured to generate the first reference voltage.

### Claim 12 (depends on 11)

The capacitor digital-to-analog converter of claim 11, wherein the reference voltage generator includes:
an amplifier including a first input terminal receiving an input voltage, a second input terminal connected to a first node, and an output terminal;
a transistor connected between a power supply voltage and a second node outputting the first reference voltage, and including a control electrode connected to the output terminal of the amplifier;
a first resistor connected between the second node and the first node;
a second resistor connected between the first node and a ground voltage; and
a decoupling capacitor connected between the second node and the ground voltage.

### Claim 13 (depends on 12)

The capacitor digital-to-analog converter of claim 12, wherein the second reference voltage is a ground voltage.

### Claim 14 (depends on 1)

The capacitor digital-to-analog converter of claim 1, further comprising:
a decoder logic circuit configured to generate the first input digital signal based on the internal clock signal.

### Claim 15 (depends on 1)

The capacitor digital-to-analog converter of claim 1, further comprising:
a second capacitor array including a plurality of capacitors, and configured to generate a second summation voltage based on the first reference voltage and the second reference voltage, the plurality of capacitors in the second capacitor array being connected to a second summation node and having different capacitances, the second summation voltage corresponding to a second input digital signal; and
a second reset circuit configured to initialize the second summation node based on the random reset control signal and a change in the second input digital signal, and
wherein the output buffer is configured to generate the first analog output voltage and a second analog output voltage by buffering the first summation voltage and the second summation voltage.

### Claim 16 (depends on 15)

The capacitor digital-to-analog converter of claim 15, wherein the first analog output voltage and the second analog output voltage are a pair of differential signals.

### Claim 17 (depends on 15)

The capacitor digital-to-analog converter of claim 15, wherein the second input digital signal is obtained by inverting the first input digital signal.

### Claim 18 (depends on 1)

The capacitor digital-to-analog converter of claim 1, wherein a phase of the internal clock signal and a phase of the reset control signal are opposite to each other.

### Claim 19

An integrated circuit comprising:
an internal circuit; and
a capacitor digital-to-analog converter (CDAC) configured to perform a digital-to-analog conversion on at least one of an input and an output of the internal circuit, and
wherein the capacitor digital-to-analog converter includes:
a clock generator configured to generate an internal clock signal and a reset control signal based on an external clock signal, the internal clock signal being regularly toggled, the reset control signal being regularly toggled;
a random reset control signal generator configured to generate a random reset control signal based on the reset control signal, the random reset control signal being irregularly toggled;
a first capacitor array including a plurality of capacitors, and configured to generate a first summation voltage based on a first reference voltage and a second reference voltage, the plurality of capacitors in the first capacitor array being connected to a first summation node and having different capacitances, the first summation voltage corresponding to a first input digital signal;
a first reset circuit configured to initialize the first summation node based on the random reset control signal and a change in the first input digital signal; and
an output buffer configured to generate a first analog output voltage by buffering the first summation voltage,
wherein the capacitor digital-to-analog converter is configured to operate in a reset phase for initializing the first summation node, and during the reset phase, a value of the first input digital signal sequentially increases based on the internal clock signal.

### Claim 20

A capacitor digital-to-analog converter (CDAC) comprising:
a clock generator configured to generate an internal clock signal and a reset control signal based on an external clock signal, the internal clock signal being regularly toggled during a reset phase and a conversion phase, the reset control signal being regularly toggled during the reset phase and having a deactivation state during the conversion phase;
a random reset control signal generator configured to generate a random reset control signal based on the internal clock signal and the reset control signal, the random reset control signal being irregularly toggled during the reset phase and having the deactivation state during the conversion phase;
a capacitor array configured to generate a summation voltage corresponding to an input digital signal based on a reference voltage and a ground voltage, the capacitor array including:
first to N-th capacitors connected to a summation node and having different capacitances, where N is a natural number greater than or equal to two; and
first to N-th switches connected to the first to N-th capacitors;
a reference voltage generator configured to generate the reference voltage, and including a decoupling capacitor;
a decoder logic circuit configured to generate the input digital signal based on the internal clock signal;
a reset circuit configured to initialize the summation node based on a reset voltage, the random reset control signal and a change in the input digital signal during the reset phase; and
an output buffer configured to generate an analog output voltage by buffering the summation voltage,
wherein, during the reset phase, a value of the input digital signal sequentially increases based on the internal clock signal, a voltage level of the summation voltage is initialized to a voltage level of the reset voltage in response to the random reset control signal having an activation state, and the voltage level of the summation voltage sequentially increases based on the input digital signal in response to the random reset control signal having the deactivation state, and
wherein, during the conversion phase, the input digital signal has a target value for a digital-to-analog conversion, and the summation voltage has a target voltage level corresponding to the target value.