# US 12,113,539 B1 · Field programmable gate array with external phase-locked loop

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- Number: US 12,113,539 B1
- Document ID: US12113539B1
- Status: Granted
- Kind: B1
- Application number: 18/067,332
- Filed: 2022-12-16
- Granted: 2024-10-08
- Earliest claimed: 2018-11-05
- Assignees: HFT Solutions, LLC
- Applicants: HFT Solutions, LLC
- Inventors: Nima Badizadegan
- Web page: https://patentgrep.com/patent/US12113539B1

## CPC

- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- H03L 7/07: using several loops, e.g. for redundant clock signal generation
- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H03L 7/0812: {and where no voltage or current controlled oscillator is used}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence)
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H04J 3/0658: {Clock or time synchronisation among packet nodes}
- H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)}
- G06F 2117/04: Clock gating
- H03L 2207/50: All digital phase-locked loop
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

## Claims

### Claim 1

A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
(a) receiving, by a field programmable array, a clock signal;
(b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
(c) generating a receiver side clock signal;
(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
(f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
(g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
(h) generating, using the phase lock loop, a second clock signal;
(i) generating a transmitter side clock signal derived from the second clock signal; and
(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
wherein steps (a)-(j) are performed without use of clock domain crossing operations.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second serial data stream comprises order entry data, and the set of operations comprises a trading algorithm, comprising steps of:
(1) parsing market data;
(2) performing mathematical operations on at least a portion of the market data; and
(3) generating order packets using at least an output of (2).

### Claim 3 (depends on 1)

The method of claim 1, wherein step (h) further comprises:
(k) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:
(A) generating, by an adjustable oscillator in the field programmable gate array system, an interim second clock signal;
(B) generating the feedback clock signal based on the interim second clock signal;
(C) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal;
(D) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;
(E) determining, by the phase controller, interim adjustment information based on the first output; and
(F) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;
wherein, the adjustable oscillator adjusts the interim second clock signal based on the interim adjustment information,
wherein steps (A) through (F) are repeated until the first output of the phase detector is below the first threshold level.

### Claim 4

A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
(a) receiving, by a field programmable array, a clock signal;
(b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
(c) generating a receiver side clock signal;
(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
(f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
(g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
(h) generating, using the phase lock loop, a second clock signal;
(i) generating a transmitter side clock signal derived from the second clock signal; and
(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
wherein steps (a)-(j) are performed without use of clock domain crossing circuits.

### Claim 5 (depends on 4)

The method of claim 4, wherein the second serial data stream comprises order entry data, and the set of operations comprises a trading algorithm, comprising steps of:
(1) parsing market data;
(2) performing mathematical operations on at least a portion of the market data; and
(3) generating order packets using at least an output of (2).

### Claim 6 (depends on 4)

The method of claim 4, wherein step (h) further comprises:
(k) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:
(A) generating, by an adjustable oscillator in the field programmable gate array system, an interim second clock signal;
(B) generating the feedback clock signal based on the interim second clock signal;
(C) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal;
(D) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;
(E) determining, by the phase controller, interim adjustment information based on the first output; and
(F) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;
wherein, the adjustable oscillator adjusts the interim second clock signal based on the interim adjustment information,
wherein steps (A) through (F) are repeated until the first output of the phase detector is below the first threshold level.

### Claim 7

A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
(a) receiving, by a field programmable array, a clock signal;
(b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
(c) generating a receiver side clock signal;
(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
(f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
(g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
(h) generating, using the phase lock loop, a second clock signal;
(i) generating a transmitter side clock signal derived from the second clock signal; and
(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
wherein the field programmable gate array system includes clock domain crossing circuitry and steps (a)-(j) are performed without use of the clock domain crossing circuitry.

### Claim 8 (depends on 7)

The method of claim 7, wherein the second serial data stream comprises order entry data, and the set of operations comprises a trading algorithm, comprising steps of:
(1) parsing market data;
(2) performing mathematical operations on at least a portion of the market data; and
(3) generating order packets using at least an output of (2).

### Claim 9 (depends on 7)

The method of claim 7, wherein step (h) further comprises:
(k) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:
(A) generating, by an adjustable oscillator in the field programmable gate array system, an interim second clock signal;
(B) generating the feedback clock signal based on the interim second clock signal;
(C) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal;
(D) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;
(E) determining, by the phase controller, interim adjustment information based on the first output; and
(F) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;
wherein, the adjustable oscillator adjusts the interim second clock signal based on the interim adjustment information,
wherein steps (A) through (F) are repeated until the first output of the phase detector is below the first threshold level.

### Claim 10

A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
(a) receiving, by a field programmable array, a clock signal;
(b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
(c) generating a receiver side clock signal;
(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
(f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
(g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
(h) generating, using the phase lock loop, a second clock signal;
(i) generating a transmitter side clock signal derived from the second clock signal; and
(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
wherein a maximum delay associated with transferring data between a receiver side clock domain associated with the receiver side clock signal and a transmitter side clock domain associated with the transmitter side clock signal is less than 1 clock cycle.

### Claim 11 (depends on 10)

The method of claim 10, wherein the second serial data stream comprises order entry data, and the set of operations comprises a trading algorithm, comprising steps of:
(1) parsing market data;
(2) performing mathematical operations on at least a portion of the market data; and
(3) generating order packets using at least an output of (2).

### Claim 12 (depends on 10)

The method of claim 10, wherein step (h) further comprises:
(k) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:
(A) generating, by an adjustable oscillator in the field programmable gate array system, an interim second clock signal;
(B) generating the feedback clock signal based on the interim second clock signal;
(C) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal;
(D) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;
(E) determining, by the phase controller, interim adjustment information based on the first output; and
(F) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;
wherein, the adjustable oscillator adjusts the interim second clock signal based on the interim adjustment information,
wherein steps (A) through (F) are repeated until the first output of the phase detector is below the first threshold level.

### Claim 13

A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
(a) receiving, by a field programmable array, a clock signal;
(b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
(c) generating a receiver side clock signal;
(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
(f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
(g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the transmitter side clock signal to generate a second plurality of parallel data streams;
(h) generating, using the phase lock loop, a second clock signal;
(i) generating a transmitter side clock signal derived from the second clock signal;
and
(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
wherein steps (a)-(j) are performed without clock domain crossing operations.

### Claim 14 (depends on 13)

The method of claim 13, wherein the second serial data stream comprises order entry data, and the set of operations comprises a trading algorithm, comprising steps of:
(1) parsing market data;
(2) performing mathematical operations on at least a portion of the market data; and
(3) generating order packets using at least an output of (2).

### Claim 15 (depends on 13)

The method of claim 13, wherein step (h) further comprises:
(k) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:
(A) generating, by an adjustable oscillator in the field programmable gate array system, the second clock signal;
(B) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal obtained from the second clock signal;
(C) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;
(D) determining, by the phase controller, interim adjustment information based on the first output; and
(E) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;
wherein, the adjustable oscillator adjusts the second clock signal based on the interim adjustment information,
wherein steps (A) through (E) are repeated until the first output of the phase detector is below the first threshold level.

### Claim 16

A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
(a) receiving, by a field programmable array, a clock signal;
(b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
(c) generating a receiver side clock signal;
(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
(f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
(g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the transmitter side clock signal to generate a second plurality of parallel data streams;
(h) generating, using the phase lock loop, a second clock signal;
(i) generating a transmitter side clock signal derived from the second clock signal;
and
(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
wherein steps (a)-(j) are performed without use of clock domain crossing circuits.

### Claim 17 (depends on 16)

The method of claim 16, wherein the second serial data stream comprises order entry data, and the set of operations comprises a trading algorithm, comprising steps of:
(1) parsing market data;
(2) performing mathematical operations on at least a portion of the market data; and
(3) generating order packets using at least an output of (2).

### Claim 18 (depends on 16)

The method of claim 16, wherein step (h) further comprises:
(k) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:
(A) generating, by an adjustable oscillator in the field programmable gate array system, an interim second clock signal;
(B) generating the feedback clock signal based on the interim second clock signal;
(C) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal;
(D) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;
(E) determining, by the phase controller, interim adjustment information based on the first output; and
(F) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;
wherein, the adjustable oscillator adjusts the interim second clock signal based on the interim adjustment information,
wherein steps (A) through (F) are repeated until the first output of the phase detector is below the first threshold level.

### Claim 19

A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
(a) receiving, by a field programmable array, a clock signal;
(b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
(c) generating a receiver side clock signal;
(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
(f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
(g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the transmitter side clock signal to generate a second plurality of parallel data streams;
(h) generating, using the phase lock loop, a second clock signal;
(i) generating a transmitter side clock signal derived from the second clock signal;
and
(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
wherein the field programmable gate array system includes clock domain crossing circuitry and steps (a)-(j) are performed without use of clock domain crossing circuitry.

### Claim 20 (depends on 19)

The method of claim 19, wherein the second serial data stream comprises order entry data, and the set of operations comprises a trading algorithm, comprising steps of:
(1) parsing market data;
(2) performing mathematical operations on at least a portion of the market data; and
(3) generating order packets using at least an output of (2).

### Claim 21 (depends on 19)

The method of claim 19, wherein step (h) further comprises:
(k) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:
(A) generating, by an adjustable oscillator in the field programmable gate array system, the second clock signal;
(B) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal obtained from the second clock signal;
(C) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;
(D) determining, by the phase controller, interim adjustment information based on the first output; and
(E) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;
wherein, the adjustable oscillator adjusts the second clock signal based on the interim adjustment information,
wherein steps (A) through (E) are repeated until the first output of the phase detector is below the first threshold level.

### Claim 22

A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
(a) receiving, by a field programmable array, a clock signal;
(b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
(c) generating a receiver side clock signal;
(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
(f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
(g) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams using the transmitter side clock signal to generate a second plurality of parallel data streams;
(h) generating, using the phase lock loop, a second clock signal;
(i) generating a transmitter side clock signal derived from the second clock signal; and
(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
wherein a maximum delay associated with transferring data between a receiver side clock domain associated with the receiver side clock signal and a transmitter side clock domain associated with the transmitter side clock signal is less than 1 clock cycle.

### Claim 23 (depends on 22)

The method of claim 22, wherein the second serial data stream comprises order entry data, and the set of operations comprises a trading algorithm, comprising steps of:
(1) parsing market data;
(2) performing mathematical operations on at least a portion of the market data; and
(3) generating order packets using at least an output of (2).

### Claim 24 (depends on 22)

The method of claim 22, wherein step (h) further comprises:
(k) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:
(A) generating, by an adjustable oscillator in the field programmable gate array system, the second clock signal;
(B) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal obtained from the second clock signal;
(C) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;
(D) determining, by the phase controller, interim adjustment information based on the first output; and
(E) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;
wherein, the adjustable oscillator adjusts the second clock signal based on the interim adjustment information,
wherein steps (A) through (E) are repeated until the first output of the phase detector is below the first threshold level.

### Claim 25

A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
(a) receiving, by a field programmable array, a clock signal;
(b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
(c) generating a receiver side clock signal;
(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
(f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
(g) performing, by the computational circuitry, a first set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
(h) generating, using the phase lock loop, a second clock signal;
(i) generating a transmitter side clock signal derived from the second clock signal;
and
(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
wherein steps (a)-(j) are performed without use of clock domain crossing operations.

### Claim 26 (depends on 25)

The method of claim 25, wherein the second serial data stream comprises order entry data, and the set of operations comprises a trading algorithm, comprising steps of:
(1) parsing market data;
(2) performing mathematical operations on at least a portion of the market data; and
(3) generating order packets using at least an output of (2).

### Claim 27 (depends on 25)

The method of claim 25, wherein step (h) further comprises:
(k) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:
(A) generating, by an adjustable oscillator in the field programmable gate array system, the second clock signal;
(B) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal obtained from the second clock signal;
(C) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;
(D) determining, by the phase controller, interim adjustment information based on the first output; and
(E) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;
wherein, the adjustable oscillator adjusts the second clock signal based on the interim adjustment information,
wherein steps (A) through (E) are repeated until the first output of the phase detector is below the first threshold level.

### Claim 28

A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
(a) receiving, by a field programmable array, a clock signal;
(b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
(c) generating a receiver side clock signal;
(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
(f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
(g) performing, by the computational circuitry, a first set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
(h) generating, using the phase lock loop, a second clock signal;
(i) generating a transmitter side clock signal derived from the second clock signal;
and
(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
wherein steps (a)-(j) are performed without use of clock domain crossing circuits.

### Claim 29 (depends on 28)

The method of claim 28, wherein the second serial data stream comprises order entry data, and the set of operations comprises a trading algorithm, comprising steps of:
(1) parsing market data;
(2) performing mathematical operations on at least a portion of the market data; and
(3) generating order packets using at least an output of (2).

### Claim 30 (depends on 28)

The method of claim 28, wherein step (h) further comprises:
(k) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:
(A) generating, by an adjustable oscillator in the field programmable gate array system, the second clock signal;
(B) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal obtained from the second clock signal;
(C) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;
(D) determining, by the phase controller, interim adjustment information based on the first output; and
(E) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;
wherein, the adjustable oscillator adjusts the second clock signal based on the interim adjustment information,
wherein steps (A) through (E) are repeated until the first output of the phase detector is below the first threshold level.

### Claim 31

A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
(a) receiving, by a field programmable array, a clock signal;
(b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
(c) generating a receiver side clock signal;
(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
(f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
(g) performing, by the computational circuitry, a first set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
(h) generating, using the phase lock loop, a second clock signal;
(i) generating a transmitter side clock signal derived from the second clock signal; and
(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
wherein the field programmable gate array system includes clock domain crossing circuitry and steps (a)-(j) are performed without use of clock domain crossing circuitry.

### Claim 32 (depends on 31)

The method of claim 31, wherein the second serial data stream comprises order entry data, and the set of operations comprises a trading algorithm, comprising steps of:
(1) parsing market data;
(2) performing mathematical operations on at least a portion of the market data; and
(3) generating order packets using at least an output of (2).

### Claim 33 (depends on 31)

The method of claim 31, wherein step (h) further comprises:
(k) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:
(A) generating, by an adjustable oscillator in the field programmable gate array system, the second clock signal;
(B) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal obtained from the second clock signal;
(C) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;
(D) determining, by the phase controller, interim adjustment information based on the first output; and
(E) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;
wherein, the adjustable oscillator adjusts the second clock signal based on the interim adjustment information,
wherein steps (A) through (E) are repeated until the first output of the phase detector is below the first threshold level.

### Claim 34

A method for processing a first serial data stream comprising market data, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:
(a) receiving, by a field programmable array, a clock signal;
(b) receiving, by a deserializer in the field programmable gate array, the first serial data stream;
(c) generating a receiver side clock signal;
(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;
(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;
(f) transmitting, from the field programmable gate array to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;
(g) performing, by the computational circuitry, a first set of operations on at least a portion of the first plurality of parallel data streams using the receiver side clock signal to generate a second plurality of parallel data streams;
(h) generating, using the phase lock loop, a second clock signal;
(i) generating a transmitter side clock signal derived from the second clock signal; and
(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams and the transmitter side clock signal,
wherein a maximum delay associated with transferring data between a receiver side clock domain associated with the receiver side clock signal and a transmitter side clock domain associated with the transmitter side clock signal is less than 1 clock cycle.

### Claim 35 (depends on 34)

The method of claim 34, wherein the second serial data stream comprises order entry data, and the set of operations comprises a trading algorithm, comprising steps of:
(1) parsing market data;
(2) performing mathematical operations on at least a portion of the market data; and
(3) generating order packets using at least an output of (2).

### Claim 36 (depends on 34)

The method of claim 34, wherein step (h) further comprises:
(k) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:
(A) generating, by an adjustable oscillator in the field programmable gate array system, the second clock signal;
(B) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal obtained from the second clock signal;
(C) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;
(D) determining, by the phase controller, interim adjustment information based on the first output; and
(E) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;
wherein, the adjustable oscillator adjusts the second clock signal based on the interim adjustment information,
wherein steps (A) through (E) are repeated until the first output of the phase detector is below the first threshold level.