# US 12,113,538 B2 · Error detection and compensation for a multiplexing transmitter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,538 B2 - Document ID: US12113538B2 - Status: Granted - Kind: B2 - Application number: 17/027,539 - Filed: 2020-09-21 - Published: 2021-01-07 - Granted: 2024-10-08 - Earliest claimed: 2018-09-27 - Assignees: MACOM Technology Solutions Holdings, Inc. - Applicants: MACOM Technology Solutions Holdings, Inc. - Inventors: Naga Rajesh Doppalapudi; Echere Iroaga - Web page: https://patentgrep.com/patent/US12113538B2 ## CPC - H03K 5/1565: {the output pulses having a constant duty cycle} - H04L 25/028: {Arrangements specific to the transmitter end} - H03K 5/05: by the use of clock signals or other time reference signals - H03K 5/135: by the use of time reference signals, e.g. clock signals - H04L 25/0264: {Arrangements for coupling to transmission lines (duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878)} - H04L 27/368: {adaptive predistortion} - H03K 2005/00286: {Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency} - H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error. ## Claims ### Claim 1 A system for reducing error associated with a transmitter, comprising: an error detector circuit configured to measure a quadrature error for a clock associated with the transmitter to generate first error detector information based on a first clock pattern for a first output generated by the transmitter in response to a defined bit pattern, and generate second error detector information based on a second clock pattern for a second output generated by the transmitter in response to an inverted version of the defined bit pattern, wherein the error detector circuit is further configured to determine a first average value of the first error detector information and a second average value of the second error detector information, determine a differential average value of the first average value and the second average value based on a comparison of the first average value to the second average value, and determine an error detector output based on the differential average value; and a quadrature error correction circuit configured to adjust the clock associated with the transmitter based on the error detector output. ### Claim 2 (depends on 1) The system of claim 1, wherein the error detector circuit is configured to measure the quadrature error for an in-phase clock associated with the transmitter to generate the error detector output based on an in-phase clock pattern for an output generated by the transmitter in response to the defined bit pattern. ### Claim 3 (depends on 1) The system of claim 1, wherein the error detector circuit is configured to measure the quadrature error for a quadrature clock associated with the transmitter to generate the error detector output based on a quadrature clock pattern for an output generated by the transmitter in response to the defined bit pattern. ### Claim 4 (depends on 1) The system of claim 1, wherein the error detector circuit is configured to measure a quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. ### Claim 5 (depends on 4) The system of claim 4, wherein the quadrature error correction circuit is further configured to adjust a phase shift between the in-phase clock and the quadrature clock based on the quadrature error. ### Claim 6 (depends on 1) The system of claim 1, wherein the error detector circuit comprises an accumulator, the accumulator configured to accumulate differential average values, comprising the differential average value, based on a first error detector stream and a second error detector stream, and convert the differential average values to generate the error detector output, wherein the first error detector stream is generated based on the defined bit pattern and comprises the first error detector information, and wherein the second error detector stream is generated based on the inverted version of the defined bit pattern and comprises the second error detector information. ### Claim 7 (depends on 6) The system of claim 6, wherein the accumulator is configured to generate the error detector output, comprising an error detector output pattern, based on the conversion of the differential average values. ### Claim 8 (depends on 1) The system of claim 1, wherein the quadrature error correction circuit is configured to adjust the clock based on the differential average value determined from the comparison of the first average value of the first error detector information and the second average value of the second error detector information. ### Claim 9 A system for reducing errors associated with a transmitter, comprising: an error detector circuit configured to measure quadrature error between an in-phase clock and a quadrature clock associated with the transmitter to generate an error detector output based on a clock pattern for output generated by the transmitter in response to a defined data input bit pattern; and a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on the quadrature error, wherein a phase correct version of the defined data input bit pattern is transmitted as output from the transmitter. ### Claim 10 (depends on 9) The system of claim 9, wherein the error detector circuit is further configured to measure duty cycle error for the in-phase clock associated with the transmitter to generate the error detector output. ### Claim 11 (depends on 10) The system of claim 10, further comprising a duty cycle correction circuit configured to adjust the in-phase clock associated with the transmitter based on the duty cycle error. ### Claim 12 (depends on 9) The system of claim 9, wherein the error detector circuit is further configured to measure duty cycle error for the quadrature clock associated with the transmitter to generate the error detector output. ### Claim 13 (depends on 12) The system of claim 12, further comprising a duty cycle correction circuit configured to adjust the quadrature clock associated with the transmitter based on the duty cycle error. ### Claim 14 (depends on 9) The system of claim 9, wherein the error detector output is a first error detector output, the clock pattern is a first clock pattern, and the output is a first output, and wherein the error detector circuit is further configured to measure a quadrature error between the in-phase clock and the quadrature clock to generate a second error detector output based on a second clock pattern for a second output generated by the transmitter in response to an inverted version of the defined bit pattern. ### Claim 15 (depends on 14) The system of claim 14, wherein the error detector circuit is configured to determine an average of the first error detector output and the second error detector output. ### Claim 16 (depends on 15) The system of claim 15, wherein the quadrature error correction circuit is configured to adjust the phase shift between the in-phase clock and the quadrature clock based on the average of the first error detector output and the second error detector output. ### Claim 17 A system for reducing error associated with a transmitter, comprising: an error detector circuit configured to measure an error for a clock associated with the transmitter, wherein the error detector generates an error detector output based on a clock pattern for output generated by the transmitter in response to a defined data input bit pattern, wherein a chosen calibration mode is selected from a plurality of different calibration modes and the defined data input bit pattern is based upon the chosen calibration mode, wherein the plurality of different calibration modes comprises a first type of calibration mode in which a first type of error is measured and a second type of calibration mode in which a second type of error is measured; and an error correction circuit configured to adjust the clock associated with the transmitter based on the error detector output, wherein a phase correct version of the defined data input bit pattern is transmitted as output from the transmitter. ### Claim 18 (depends on 17) The system of claim 17, wherein the error detector circuit is configured to measure a duty cycle error. ### Claim 19 (depends on 17) The system of claim 17, wherein the error detector circuit is configured to measure a quadrature error. ### Claim 20 (depends on 17) The system of claim 17, wherein the error correction circuit is configured to adjust a clock based on an average of a first error detector output and a second error detector output. ### Claim 21 (depends on 17) The system of claim 17, wherein the transmitter is a multiplexing transmitter. ### Claim 22 (depends on 17) The system of claim 17, wherein the plurality of different types of calibration modes comprises one type of calibration mode in which a duty cycle correction is performed and another type of calibration mode in which a quadrature error correction is performed. ### Claim 23 (depends on 17) The system of claim 17, wherein the detector circuit generates an N-bit pattern based on the error detector output, wherein the N-bit pattern is a set of bits indicating error correction. ### Claim 24 (depends on 23) The system of claim 23, wherein the error correction circuit adjusts the clock based on an amount of duty cycle error indicated by the error detected output N-bit pattern. ### Claim 25 (depends on 17) The system of claim 17, the clock is digitally delayed to manage a rise time and a fall time of the clock. ### Claim 26 (depends on 17) The system of claim 17, wherein the error correction circuit comprises: a current mode logic (CML) buffer wherein a version of a signal associated with the clock is processed by the CML buffer to manage a rise time and a fall time; and a digital-to-converter (DAC) can convert a N-bit pattern from a digital signal to an analog signal. ### Claim 27 A method comprising: choosing a calibration mode selected from a plurality of different types of calibration modes, wherein the chosen calibration mode comprises a first error measurement associated with a first type of clock in a plurality of clocks, and another one of the plurality of different types of calibration modes comprises a second error measurement associated with a second type of clock in the plurality of clocks, wherein the first type of clock and second type of clock are substantially similar frequencies with respect to one another; measuring an error associated with a transmitter according to the chosen calibration mode; generating an error detector output based on an output generated in response to a defined data input bit pattern, wherein the defined data input bit pattern is based upon the chosen calibration mode; and adjusting the first type of clock in the plurality of clocks based on the error detector output. ### Claim 28 (depends on 27) The method of claim 27, wherein the defined data input bit pattern is one of a plurality of defined data input bit patterns and the defined data input bit pattern is an inverse of another one of the plurality of defined data input patterns, wherein a phase correct version of the defined data input bit pattern is transmitted as output from the transmitter. ### Claim 29 (depends on 27) The method of claim 27, wherein the plurality of different types of calibration modes comprise one type of calibration mode in which a duty cycle correction is performed and another type of calibration mode in which a quadrature error correction is performed. ### Claim 30 (depends on 27) The method of claim 27, wherein the adjusting the first type of clock is based on an average of a first error detector output and a second error detector output. ### Claim 31 (depends on 27) The method of claim 27, further comprising generating an N-bit pattern based on the error detector output, wherein the N-bit pattern is a set of bits indicating error correction and the adjusting the clock is based upon the N-bit pattern. ### Claim 32 (depends on 27) The method of claim 27, wherein the adjusting the first type of clock comprises performing interpolation based upon a defined code, wherein the interpolation comprises generating a modified clock signal. ### Claim 33 A method comprising: providing a plurality of defined bit patterns to a transmitter; converting the defined bit patterns into a plurality of output data streams based upon a clock provided to the transmitter, wherein the converting further comprises converting a first one of the plurality of output data streams based on a first clock pattern, wherein the first one of the plurality of output data streams is associated with a first one of the plurality of defined bit patterns, and converting a second one of the plurality of output data streams based on a second clock pattern, wherein the second one of the plurality of output data streams is associated with a second one of the plurality of defined bit patterns, detecting a plurality of errors for the clock, wherein respective ones of the plurality of errors are associated with respective ones of the plurality of defined bit patterns, wherein the detecting comprises measuring the plurality of errors; generating error detection output information, wherein a first portion of the error detection output information is associated with the measuring of a first one of the plurality of errors and a second portion of the error detection output information is associated with the measuring of a second one of the plurality of errors; and adjusting the clock based on the results of the measuring the plurality of errors, including the first error detection output information and the second error detection information. ### Claim 34 (depends on 33) The method of claim 33, wherein one of the plurality of errors is associated with a duty cycle error. ### Claim 35 (depends on 33) The method of claim 33, wherein one of the plurality of errors is associated with a quadrature error. ### Claim 36 (depends on 33) The method of claim 33, further comprising: determining a first average value of the first portion of error detection output information; determining a second average value of the second portion of the error detection output information; and determining a differential average value of the first average value and the second average value based on a comparison of the first average value to the second average value, wherein the generating the error detection output information is based on the differential average value. ### Claim 37 (depends on 33) The method of claim 33, the plurality of errors comprises a first type of error and a second type of error, wherein in a first mode the first type of error is detected and in a second mode the second type of error is detected. ### Claim 38 (depends on 33) The method of claim 33, wherein the first one of the plurality of defined bit patterns is an inverted version of the second one of the plurality of defined bit patterns. ### Claim 39 (depends on 33) The method of claim 33, wherein adjusting the clock comprises adjusting an in-phase clock. ### Claim 40 (depends on 33) The method of claim 33, wherein adjusting the clock comprises adjusting a quadrature clock. ### Claim 41 (depends on 33) The method of claim 33, wherein the adjusting comprises adjusting a phase shift between an in-phase clock and a quadrature clock. ### Claim 42 (depends on 33) The method of claim 33, wherein the adjusting comprises employing resistive feedback to convert a modified clock to a first complementary metal oxide silicon (CMOS) clock output for the transmitter.