# US 12,113,536 B2 · High speed sampling circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,113,536 B2
- Document ID: US12113536B2
- Status: Granted
- Kind: B2
- Application number: 18/253,050
- Filed: 2021-03-24
- Published: 2023-12-28
- Granted: 2024-10-08
- Earliest claimed: 2020-12-01
- Assignees: Shenzhen Pango Microsystems Co., Ltd
- Applicants: Shenzhen Pango Microsystems Co., Ltd
- Inventors: Guangyao You; Yuanjun Liang
- Web page: https://patentgrep.com/patent/US12113536B2

## CPC

- H03K 3/35613: {the input circuit having a differential configuration}
- H03K 3/356139: {with synchronous operation}
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 27/02: Sample-and-hold arrangements (G11C27/04 takes precedence)
- H03M 1/1245: {Details of sampling arrangements or methods}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A high-speed sampling circuit is disclosed which comprises a sampling module for amplifying a differential input signal; a latch module for latching the differential output signal of the sampling module; a first control module for controlling the sampling module under a first clock signal; a second control module for controlling the latch module under a second clock signal; a third control module for controlling control the output of the differential output signal under the second clock signal. The high-speed sampling circuit of the disclosure, after sampling the differential input signal, the sampling module outputs it to the latch module and controls the latch module to output the differential output signal, compared to the existing two-stage sampling module, it saves the transmission delay of the two-stage sampling module and can improve the performance of the high-speed sampling band of the signal.

## Claims

### Claim 1

A high-speed sampling circuit comprising:
a sampling module configured for amplifying a differential input signal;
a latch module configured for latching a differential output signal of the sampling module;
a first control module configured for controlling the sampling module under a first clock signal;
a second control module configured for controlling the latch module under a second clock signal; and
a third control module for controlling the output of the differential output signal under the second clock signal;
wherein during a first stage from time point T0 to time point T1, both the first clock signal and the second clock signal are each 0, both the sampling module and the latch module are turned off, and both the first differential output node and the second differential output node are operative to be pulled up to a power supply voltage;
wherein during a second stage from time point T1 to time point T2, both the first clock signal and the second clock signal are each 1, both the sampling module and the latch module are turned on, and a voltage difference between the first differential input node and the second differential input node is operative to cause the latch module to enter an unbalanced state;
wherein during a third stage from time point T2 to time point T3, the first clock signal is 0, the sampling module is turned off, and the unbalanced state of two branches of the latch module is amplified through a positive feedback, so that an input state sampled in the T1 to T2 stage is output through the first differential output node and the second differential output node;
wherein during a fourth stage from time point T3 to time point T4, both the first clock signal and the second clock signal are each 0, and the high-speed sampling circuit is operative to return to the reset state in the first stage from the time point T0 to the time point T1.

### Claim 2 (depends on 1)

The high-speed sampling circuit according to claim 1, wherein the high-speed sampling circuit further includes a differential output terminal configured for outputting the differential output signal; wherein the sampling module, the latch module, and the third control module are each connected to the differential output terminal.

### Claim 3 (depends on 1)

The high-speed sampling circuit according to claim 1, wherein the sampling module and the first control module are connected to a first control node.

### Claim 4 (depends on 3)

The high-speed sampling circuit according to claim 3, wherein the latch module and the second control module are connected to a second control node.

### Claim 5 (depends on 4)

The high-speed sampling circuit according to claim 4, wherein
the first control module includes a fifth NMOS transistor, with a drain of the fifth NMOS transistor connected to the first control node, a gate of the fifth NMOS transistor M5 is connected to the first clock signal, and a source of the fifth NMOS transistor is connected to a ground terminal;
the second control module includes a sixth NMOS transistor, with a drain of the sixth NMOS transistor connected to the second control node, a gate of the sixth NMOS transistor is connected to the second clock signal, and a source of the sixth NMOS transistor is connected to another ground terminal.

### Claim 6 (depends on 4)

The high-speed sampling circuit according to claim 4, wherein
the third control module includes a forty-one PMOS transistor and a forty-two PMOS transistor, source of the forty-one PMOS transistor is connected to a power supply, a gate of the forty-one PMOS transistor is connected to the second clock signal, a drain of the forty-one PMOS transistor is connected to a second differential output node; a source of the forty-two PMOS transistor is connected to the power supply, a gate of the forty-two PMOS transistor is connected to the second clock signal, and a drain of the forty-two PMOS transistor is connected to a first differential output node.

### Claim 7 (depends on 4)

The high-speed sampling circuit according to claim 4, wherein
the sampling module includes an eleventh NMOS transistor and a twelfth NMOS transistor, a drain of the eleventh NMOS transistor is connected to a second differential output node, a gate of the eleventh NMOS transistor is connected to a first differential input node, a source of the eleventh NMOS transistor is connected to a source of the twelfth NMOS transistor at the first control node, a gate of the twelfth NMOS transistor is connected to a second differential input node, and a drain of the twelfth NMOS transistor is connected to the first differential output node.

### Claim 8 (depends on 4)

The high-speed sampling circuit according to claim 4, wherein the latch module includes a first latch branch and a second latch branch,
wherein the first latch branch includes a thirty-one PMOS transistor and a twenty-one NMOS transistor that are connected in series between the power supply and the second control node; a source of the thirty-one PMOS transistor is connected to the power supply, a gate of the thirty-one PMOS transistor is connected to a gate of the twenty-one NMOS transistor at a first differential output node, a drain of the thirty-one PMOS transistor is connected to a drain of the twenty-one NMOS transistor at a second differential output node, a source of the twenty-one NMOS transistor is connected to the second control node;
wherein the second latch branch includes a thirty-two PMOS transistor and a twenty-two NMOS transistor that are connected in series between the power supply and the second control node; a source of the thirty-two PMOS transistor is connected to the power supply, a gate of the thirty-two PMOS transistor is connected to a gate of the twenty-two NMOS transistor at the second differential output node, a drain of the thirty-two PMOS transistor is connected to a drain of the twenty-two NMOS transistor at the first differential output node, a source of the twenty-two NMOS transistor is connected to the second control node.