# US 12,113,533 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,533 B2 - Document ID: US12113533B2 - Status: Granted - Kind: B2 - Application number: 18/448,285 - Filed: 2023-08-11 - Published: 2023-11-30 - Granted: 2024-10-08 - Earliest claimed: 2019-06-06 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Naoki Takahashi - Web page: https://patentgrep.com/patent/US12113533B2 ## CPC - H03K 3/011: Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} - H03K 17/0822: {in field-effect transistor switches} - H03K 17/122: {in field-effect transistor switches} - H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 30/669: {having voltage-sensing or current-sensing structures, e.g. emulator sections or overcurrent sensing cells} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers - H10D 84/0126: {the components including insulated gates, e.g. IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H03K 2017/0806: {against excessive temperature} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes first and second insulated-gate transistors in parallel with each other, a charger-discharger, and a gate voltage correction circuit. The charger-discharger can perform first control to charge both of the gates of the first and second transistors, second control to discharge both of the gates of the first and second transistors, and third control to charge one of the gates of the first and second transistors. The gate voltage correction circuit corrects the gate voltages of the first and second transistors to eliminate the difference between those voltages in at least one of the first control, the second control, and protection operation in which the first and second transistors are forcibly kept off. ## Claims ### Claim 1 A semiconductor device comprising: a first transistor of an insulated gate type and a second transistor of an insulated gate type, the first and second transistors being connected in parallel with each other; a charger-discharger; and a gate voltage correction circuit, wherein the charger-discharger is configured to be capable of performing first control in which the charger-discharger charges both of respective gates of the first and second transistors, second control in which the charger-discharger discharges both of the respective gates of the first and second transistors, and third control in which the charger-discharger discharges only one of the respective gates of the first and second transistors, and the gate voltage correction circuit is configured to correct respective gate voltages of the first and second transistors, and protection operation in which the first and second transistors are forcibly kept off. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the gate voltage correction circuit is configured to correct the respective gate voltages of the first and second transistors so as to eliminate the difference between the respective gate voltages of the first and second transistors in each of the first control, the second control, and the protection operation. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the gate voltage correction circuit includes a first adjuster configured to adjust, in accordance with the difference between the respective gate voltages of the first and second transistors, distribution of currents that are made to flow into the gates of the first and second transistors respectively in the first control. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the gate voltage correction circuit includes a second adjuster configured to adjust, in accordance with the difference between the respective gate voltages of the first and second transistors, distribution of currents that are drawn out from the gates of the first and second transistors respectively in the second control. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the gate voltage correction circuit includes a third adjuster configured to adjust, in accordance with the difference between the respective gate voltages of the first and second transistors, distribution of currents that are drawn out from the gates of the first and second transistors respectively in the protection operation. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, comprising a single adjuster configured to be shared as the second and third adjusters. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the first and second transistors are each formed as a single split-gate device. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein a channel region of the first transistor is formed with a first channel ratio and a channel region of the second transistor is formed with a second channel ratio different from the first channel ratio. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein a channel utilization rate in active clamp operation is more than zero but less than a channel utilization rate in normal operation. ### Claim 10 (depends on 1) An electronic appliance comprising: the semiconductor device according to claim 1; and an inductive load connected to the semiconductor device.