# US 12,113,529 B2 · Electronic device and memristor-based logic gate circuit thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,529 B2 - Document ID: US12113529B2 - Status: Granted - Kind: B2 - Application number: 18/694,941 - Filed: 2022-09-28 - Published: 2024-08-15 - Granted: 2024-10-08 - Earliest claimed: 2022-02-18 - Assignees: Inspur Suzhou Intelligent Technology Co., Ltd. - Applicants: Suzhou Metabrain Intelligent Technology Co., Ltd. - Inventors: Kang Su; Fen Guo; Hongtao Man; Tuo Li - Web page: https://patentgrep.com/patent/US12113529B2 ## CPC - H03K 19/02: using specified components ({H03K19/0005 - H03K19/0021}, H03K19/003 - H03K19/0175 take precedence) - G06F 7/501: Half or full adders, i.e. basic adder cells for one denomination - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An electronic device and a memristor-based logic gate circuit thereof. In the present application, a control end of a controllable switch is connected to a negative end of an output memristor in a MAGIC-based AND logic gate, and whether a second memristor is powered on is controlled by the controllable switch. Thus, when resistance value states of two input memristors in the AND logic gate are different, the controllable switch will conduct and power on the second memristor, and the second memristor will present a low-resistance state at this time. When the resistance value states of the two input memristors are the same, the controllable switch will not conduct and the second memristor will then remain the state unchanged, i.e., presents a high-resistance state. An exclusive OR logic gate is formed by combining the two input memristors and the second memristor. ## Claims ### Claim 1 A memristor-based logic gate circuit, comprising: an AND logic gate based on a memristor-aided logic (MAGIC) auxiliary logic gate, used for realizing an operation of logic AND based on three first memristors connected in series within the AND logic gate; a first power supply, used for outputting electric energy when the AND logic gate is in a steady state; a second memristor having a first end connected to the first power supply, used for presenting a low-resistance state merely when the first power supply supplies power to itself; and a controllable switch having a first end connected to a second end of the second memristor, a second end being grounded, and a control end connected to a negative end of the first memristor as an output memristor, wherein the controllable switch is used for conducting merely when two first memristors as input memristors in the AND logic gate present different resistance value states. ### Claim 2 (depends on 1) The memristor-based logic gate circuit according to claim 1, wherein the AND logic gate based on the auxiliary logic gate MAGIC comprises a second power supply, a first control switch, a first input memristor, a second input memristor, and the output memristor; and the second power supply is connected to a first end of the first control switch, a second end of the first control switch is connected to a negative end of the first input memristor, a positive end of the first input memristor is connected to a negative end of the second input memristor, a positive end of the second input memristor is connected to a negative end of the output memristor, and a positive end of the output memristor is grounded. ### Claim 3 (depends on 2) The memristor-based logic gate circuit according to claim 2, wherein the output memristor presents a high-resistance state in an initial state. ### Claim 4 (depends on 2) The memristor-based logic gate circuit according to claim 2, wherein the first power supply comprises a power supply unit and a second control switch; the first power supply is connected to a first end of the second control switch, and a second end of the second control switch is connected to the first end of the second memristor; and the second control switch is used for being controlled to be turned off when the AND logic gate is in the steady state, so that the power supply unit outputs the electric energy. ### Claim 5 (depends on 4) The memristor-based logic gate circuit according to claim 4, wherein the second power supply and the power supply unit are a same power source. ### Claim 6 (depends on 4) The memristor-based logic gate circuit according to claim 4, wherein the first control switch and the second control switch are of a same type. ### Claim 7 (depends on 6) The memristor-based logic gate circuit according to claim 6, wherein the first control switch and the second control switch are both gated switches. ### Claim 8 (depends on 4) The memristor-based logic gate circuit according to claim 4, wherein the first control switch and the second control switch are of different types. ### Claim 9 (depends on 4) The memristor-based logic gate circuit according to claim 4, wherein the second power supply and the power supply unit are mutually independent power sources. ### Claim 10 (depends on 1) The memristor-based logic gate circuit according to claim 1, wherein the controllable switch is an N-type metal-oxide-semiconductor (NMOS). ### Claim 11 (depends on 10) The memristor-based logic gate circuit according to claim 10, wherein a threshold voltage of the N-type metal-oxide-semiconductor (NMOS) is greater than one third of a nominal voltage of the first power supply and less than a half of the nominal voltage of the first power supply. ### Claim 12 (depends on 10) The memristor-based logic gate circuit according to claim 10, wherein a drain electrode of the N-type metal-oxide-semiconductor (NMOS) is connected to the second end of the second memristor, a source electrode of the N-type metal-oxide-semiconductor (NMOS) is grounded, and a gate electrode of the N-type metal-oxide-semiconductor (NMOS) is connected to the negative end of the first memristor as the output memristor. ### Claim 13 (depends on 1) The memristor-based logic gate circuit according to claim 1, wherein the first memristor and the second memristor are of a same type. ### Claim 14 (depends on 13) The memristor-based logic gate circuit according to claim 13, wherein the first memristor and the second memristor are threshold-type memristors. ### Claim 15 (depends on 14) The memristor-based logic gate circuit according to claim 14, wherein a voltage of the first power supply is greater than a first threshold voltage of the threshold memristor and less than twice the first threshold voltage of the threshold-type memristor; and the first threshold voltage of the threshold-type memristor is a voltage threshold at which the threshold-type memristor transitions from a low-resistance state to a high-resistance state. ### Claim 16 (depends on 1) The memristor-based logic gate circuit according to claim 1, wherein the second memristor presents a high-resistance state in an initial state. ### Claim 17 (depends on 1) The memristor-based logic gate circuit according to claim 1, wherein the memristor-based logic gate circuit is configured to form a half adder circuit. ### Claim 18 (depends on 17) The memristor-based logic gate circuit according to claim 17, wherein a sum of outputs of the half adder circuit is a sum of exclusive OR operations of logic states corresponding to the resistance value states of the two first memristors as the input memristors. ### Claim 19 (depends on 17) The memristor-based logic gate circuit according to claim 17, wherein a carrying value of the half adder circuit is a dot product of logic states corresponding to the resistance value states of the two first memristors as the input memristors. ### Claim 20 An electronic device, comprising a memristor-based logic gate circuit, wherein the memristor-based logic gate circuit includes: an AND logic gate based on a memristor-aided logic (MAGIC) auxiliary logic gate, used for realizing an operation of logic AND based on three first memristors connected in series within the AND logic gate; a first power supply, used for outputting electric energy when the AND logic gate is in a steady state; a second memristor having a first end connected to the first power supply, used for presenting a low-resistance state merely when the first power supply supplies power to itself; and a controllable switch having a first end connected to a second end of the second memristor, a second end being grounded, and a control end connected to a negative end of the first memristor as an output memristor, wherein the controllable switch is used for conducting merely when two first memristors as input memristors in the AND logic gate present different resistance value states.