# US 12,113,510 B2 · Transversely-excited film bulk acoustic resonators with multiple piezoelectric membrane thicknesses on the same chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,510 B2 - Document ID: US12113510B2 - Status: Granted - Kind: B2 - Application number: 17/339,841 - Filed: 2021-06-04 - Published: 2022-08-04 - Granted: 2024-10-08 - Earliest claimed: 2021-02-03 - Assignees: Murata Manufacturing Co., Ltd. - Applicants: Murata Manufacturing Co., Ltd. - Inventors: Andrew Kay; Patrick Turner; Albert Cardona - Web page: https://patentgrep.com/patent/US12113510B2 ## CPC - H03H 9/54: comprising resonators of piezoelectric or electrostrictive material (comprising resonators using surface acoustic waves H03H9/64) - H03H 3/02: for the manufacture of piezoelectric or electrostrictive resonators or networks (H03H3/08 takes precedence) - H03H 9/02015: {Characteristics of piezoelectric layers, e.g. cutting angles} - H03H 9/02157: {Dimensional parameters, e.g. ratio between two dimension parameters, length, width or thickness} - H03H 9/02228: {Guided bulk acoustic wave devices or Lamb wave devices having interdigital transducers situated in parallel planes on either side of a piezoelectric layer} - H03H 9/13: for networks consisting of piezoelectric or electrostrictive materials (for networks using surface acoustic waves H03H9/145) - H03H 9/174: {Membranes} - H03H 9/205: having multiple resonators (crystal tuning forks H03H9/21) - H03H 9/564: {implemented with thin-film techniques} - H03H 9/568: {consisting of a ladder configuration} - H03H 2003/023: {the resonators or networks being of the membrane type} - Y10T 29/42: Piezoelectric device making - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract An acoustic resonator is fabricated with multiple piezoelectric plate thicknesses on a single chip. After conductor patterns are formed on a piezoelectric plate, the plate is bonded to a sacrificial substrate, with the conductor patterns facing the sacrificial substrate. The piezoelectric plate is then thinned to a desired thickness for shunt resonators. A mask is applied to the surface of the plate and selected areas of the piezoelectric plate are further thinned to a desired thickness for series resonators to form a thinned piezoelectric plate. A substrate with swimming pool cavities is bonded to the thinned piezoelectric plate, and the sacrificial substrate is removed. ## Claims ### Claim 1 A method for fabricating an acoustic filter with multiple piezoelectric plate thicknesses on a single chip, comprising: forming conductor patterns on a piezoelectric plate; bonding the piezoelectric plate to a sacrificial substrate, with the conductor patterns facing the sacrificial substrate; thinning the piezoelectric plate to a first thickness for shunt resonators; applying a mask and further thinning selected areas of the piezoelectric plate to a second thickness for series resonators to form a thinned piezoelectric plate; bonding a substrate with a plurality of cavities to the thinned piezoelectric plate; and removing the sacrificial substrate. ### Claim 2 (depends on 1) The method of claim 1, wherein applying the mask and further thinning selected areas includes patterning the mask to expose the selected areas and ion milling the exposed selected areas to remove a milled away thickness of the piezoelectric plate to form the second thickness for series resonators. ### Claim 3 (depends on 1) The method of claim 1, wherein the conductor patterns include interdigital transducers (IDTs) that are each on a front surface of the piezoelectric plate and that are over a respective cavity that is below a back surface of the piezoelectric plate. ### Claim 4 (depends on 3) The method of claim 3, wherein the IDTs are on membranes of the piezoelectric plate that span the plurality of cavities, respectively, and wherein non-selected areas of the piezoelectric plate have the first thickness for shunt resonators and form shunt membranes of the piezoelectric plate that are over shunt cavities of the plurality of cavities; and wherein the selected areas have the second thickness for the series resonators and form series membranes of the piezoelectric plate that are over series cavities of the plurality of cavities. ### Claim 5 (depends on 3) The method of claim 3, wherein the bonding includes flipping the piezoelectric plate so that the selected areas on a back surface of the piezoelectric plate are facing and span the series cavities and the IDTs are on a front surface of the piezoelectric plate. ### Claim 6 (depends on 3) The method of claim 3, wherein the thinning of the piezoelectric plate to a first thickness for shunt resonators includes: planarizing a front surface of the piezoelectric plate; forming the IDTs on the planarized front surface of the piezoelectric plate; planarizing a back surface of the piezoelectric plate to the first thickness for shunt resonators. ### Claim 7 (depends on 6) The method of claim 6, wherein applying the mask and further thinning selected areas of the piezoelectric plate to a second thickness for series resonators includes: masking the back surface of the piezoelectric plate having the first thickness for shunt resonators to expose only the selected areas; ion milling the exposed selected areas to remove a milled away thickness of the piezoelectric plate to form the second thickness for series resonators. ### Claim 8 (depends on 7) The method of claim 7, further comprising: flip bonding the planarized front surface of the piezoelectric plate having the IDTs to a support wafer prior to planarizing the back surface of the piezoelectric plate; flip bonding the back surface of the piezoelectric plate to the substrate using the support wafer after ion milling the masked back surface to the second thickness for series resonators; and removing the support wafer. ### Claim 9 (depends on 1) The method of claim 1, wherein bonding the piezoelectric plate to a sacrificial substrate includes: forming an adhesive layer over the front surface of the piezoelectric_plate and over the conductor patterns; and bonding the adhesive layer to the sacrificial substrate; and wherein removing the sacrificial substrate includes removing the adhesive layer. ### Claim 10 (depends on 1) The method of claim 1, further comprising tuning a frequency of the shunt and series resonators using the respective thicknesses of the shunt and series resonators such that a radio frequency signal applied to shunt IDTs and series IDTs excite different shunt and series primary shear acoustic modes in the shunt and series resonators. ### Claim 11 A method for fabricating an acoustic resonator device on a single chip, the method comprising: forming conductor patterns on a piezoelectric plate; bonding the piezoelectric plate to a sacrificial substrate using an adhesive layer between the piezoelectric plate and the sacrificial substrate, with the conductor patterns facing the sacrificial substrate; thinning the piezoelectric plate to a desired thickness for shunt resonators; applying a mask and further thinning selected areas of the piezoelectric plate to another desired thickness for series resonators to form a thinned piezoelectric plate; bonding a substrate of the single chip with swimming pool cavities to the further thinned piezoelectric plate; removing the sacrificial substrate; and removing the adhesive layer. ### Claim 12 (depends on 11) The method of claim 11, wherein applying the mask and further thinning selected areas includes patterning the mask to expose the selected areas and ion milling the exposed selected areas to remove a milled away thickness of the plate to form the desired thickness for series resonators. ### Claim 13 (depends on 11) The method of claim 11, wherein the conductor patterns include series resonator and shunt resonator interdigital transducers (IDTs), wherein each series resonator and shunt resonator IDT is on a front surface of the piezoelectric plate and is over a swimming pool cavity that is below a back surface of the piezoelectric plate. ### Claim 14 (depends on 13) The method of claim 13, wherein the series resonator and shunt resonator IDTs are on membranes of the piezoelectric plate that span the swimming pool cavities, and wherein non-selected areas of the piezoelectric plate have the desired thickness for shunt resonators and form shunt membranes of the piezoelectric plate that span shunt cavities of the swimming pool cavities; and wherein the selected areas have the desired thickness for the series resonators and form series membranes of the piezoelectric plate that span series cavities of the swimming pool cavities. ### Claim 15 (depends on 13) The method of claim 13, wherein bonding includes flipping the plate so that the selected areas on a back surface of the plate are facing and span the series cavities and the series resonator and shunt resonator IDTs are on a front surface of the plate. ### Claim 16 (depends on 13) The method of claim 13, wherein thinning the piezoelectric plate to a desired thickness for shunt resonators includes: planarizing a front surface of the plate; forming the series resonator and shunt resonator IDTs on the planarized front surface of the plate; planarizing a back surface of the plate to the desired thickness for shunt resonators. ### Claim 17 (depends on 16) The method of claim 16, wherein applying a mask and further thinning selected areas of the piezoelectric plate to a desired thickness for series resonators includes: masking the back surface of the plate having the desired thickness for shunt resonators to expose only the selected areas; ion milling the exposed selected areas to remove a milled away thickness of the plate to form the desired thickness for series resonators. ### Claim 18 (depends on 17) The method of claim 17, further comprising: flip bonding the planarized front surface of the plate having the series resonator and shunt resonator IDTs to a support wafer prior to planarizing the back surface of the plate; flip bonding the back surface of the plate to the substrate using the support wafer after ion milling the masked back surface to a desired thickness for series resonators; and removing the support wafer. ### Claim 19 (depends on 11) The method of claim 11, wherein bonding the piezoelectric plate to a sacrificial substrate includes: forming the adhesive layer over the front surface of the plate and over the conductor patterns; and bonding the adhesive layer to the sacrificial substrate. ### Claim 20 (depends on 19) The method of claim 19, wherein bonding the piezoelectric plate to a sacrificial substrate includes: forming a laser release material (LRL) on a back surface of sacrificial substrate; and bonding the adhesive layer to the LRL; and wherein removing the sacrificial substrate includes removing the LRL prior to removing the adhesive layer.