# US 12,113,501 B2 · Ultra-wideband attenuator with low phase variation and improved stability with respect to temperature variations

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- Number: US 12,113,501 B2
- Document ID: US12113501B2
- Status: Granted
- Kind: B2
- Application number: 17/769,898
- Filed: 2020-11-29
- Published: 2022-11-24
- Granted: 2024-10-08
- Earliest claimed: 2019-12-01
- Assignees: Rafael Advanced Defense Systems Ltd.
- Applicants: Rafael Advanced Defense Systems Ltd.
- Inventors: Samuel Jameson
- Web page: https://patentgrep.com/patent/US12113501B2

## CPC

- H03H 11/245: {using field-effect transistor}
- H03H 7/25: comprising an element controlled by an electric or magnetic variable (H03H7/27 takes precedence)
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)

## Abstract

A method for improving the stability and reducing phase variations of an ultra-wideband attenuator, with respect to temperature variations, comprising the steps of providing an attenuator implemented in π-topology and consisting of a serial path between the input and the output of the attenuator, including a first serial resistor Rs1 connected to the input, followed by a serial inductor Ls, followed by a second serial resistor Rs2 connected to the output; a first transistor T1 bridging between the input and the output, for controlling the impedance of the serial path by a first control input provided to the first transistor T1; a first parallel path between the input and ground, including a first parallel transistor T2a followed by first parallel resistor Rp1; a second parallel path between the output and ground, including a second parallel transistor T2b followed by second parallel resistor Rp2; a second control input commonly provided to first parallel transistor T2a and to the second parallel transistor T2b, for controlling the impedance of the first and second parallel paths; unifying the serial resistors to a common serial resistor Rs and splitting the serial inductor Ls to two serial inductors Ls1 and Ls2, such that one serial inductor is connected between the input and a first contract of the common serial resistor Rs and the other serial inductor is connected between the output and the other contact of the common serial resistor Rs; splitting the parallel resistor Rp1 to two smaller resistors, connecting a first smaller resistor to the input, connecting a second smaller resistor to the first smaller resistor via the first parallel transistor T2a and to ground via a third parallel transistor T3a; splitting the parallel resistor Rp2 to two smaller resistors, connecting a third smaller resistor to the output, connecting a fourth smaller resistor to the third smaller resistor via the second parallel transistor T2b and to ground via a fourth parallel transistor T3b; connecting a first feedback capacitor Cfb1 between the common point connecting between the ungrounded port of the second parallel transistor T3a and the first contract of the common serial resistor Rs and connecting a second feedback capacitor Cfb2 between the common point connecting between the ungrounded port of the fourth parallel transistor T3b and the second contract of the common serial resistor Rs; upon controlling the first and second parallel transistors T2a and T2b by the second control input, simultaneously controlling also the third and the fourth parallel transistors T3a and T3b by the second control input; controlling the first and the second control inputs to obtain a desired attenuation between the input and output of the attenuator.

## Claims

### Claim 1

A method for improving the stability and reducing phase variations of an ultra-wideband attenuator, with respect to temperature variations, comprising:
a) providing an attenuator implemented in π- topology and consisting of:
a. 1) a serial path between the input and the output of said attenuator, including a first serial resistor (Rs1) connected to said input, followed by a serial inductor (Ls), followed by a second serial resistor (Rs2) connected to said output;
a.2) a first transistor (T1) bridging between said input and said output, for controlling the impedance of said serial path by a first control input (Vc1) provided to said first transistor (T1);
a.3) a first parallel path between said input and ground, including a first parallel transistor (T2a) followed by first parallel resistor (Rp1);
a.4) a second parallel path between said output and ground, including a second parallel transistor (T2b) followed by second parallel resistor (Rp2);
a.5) a second control input (Vc2) commonly provided to first parallel transistor (T2a) and to said second parallel transistor (T2b), for controlling the impedance of said first and second parallel paths;
b) rearranging the components in said serial path by unifying said serial resistors to a common serial resistor (Rs) and splitting said serial inductor (Ls) to two serial inductors (Ls1) and (Ls2), such that one serial inductor (Ls1) is connected between said input and a first contract of said common serial resistor (Rs) and the other serial inductor (Ls2) is connected between said output and the other contact of said common serial resistor (Rs);
c) modifying the components in said first parallel path by splitting the parallel resistor (Rp1) to two smaller resistors (Rp11 and Rp12), connecting a first smaller resistor (Rp11) to the input, connecting a second smaller resistor (Rp12) to said to first smaller resistor (Rp11) via said first parallel transistor (T2a) and to ground via a third parallel transistor (T3a);
d) modifying the components in said second parallel path by splitting the parallel resistor (Rp2) to two smaller resistors (Rp21 and Rp22), connecting a third smaller resistor (Rp21) to the output, connecting a fourth smaller resistor (Rp22) to said to third smaller resistor (Rp21) via said second parallel transistor (T2b) and to ground via a fourth parallel transistor (T3b);
e) connecting a first feedback capacitor (Cfb1) between the common point connecting between the ungrounded port of said second parallel transistor (T3a) and the first contract of said common serial resistor (Rs) and connecting a second feedback capacitor (Cfb2) between the common point connecting between the ungrounded port of said fourth parallel transistor (T3b) and the second contract of said common serial resistor (Rs);
f) upon controlling said first and second parallel transistors (T2a) and (T2b) by said second control input (Vc2), simultaneously controlling also said third and said fourth parallel transistors (T3a and T3b) by said second control input (Vc2); and
g) controlling said first and said second control inputs (Vc1 and Vc2) to obtain a desired attenuation between said input and output of said attenuator.

### Claim 2 (depends on 1)

A method according to claim 1, wherein the transistors are implemented using MOSFET technology.

### Claim 3 (depends on 1)

A method according to claim 1, wherein the attenuator is implemented using differential or single-ended topology.

### Claim 4 (depends on 1)

A method according to claim 1, wherein the circuitry for implementing said attenuator is symmetrical, such that:
Rs1=Rs2;
Rp1=Rp2;
first smaller resistor=third smaller resistor;
second smaller resistor=fourth smaller resistor.

### Claim 5 (depends on 1)

A method according to claim 1, wherein optimal performance is obtained when the resistors are split to two equal smaller resistors.

### Claim 6 (depends on 1)

A method according to claim 1, wherein the phase imbalance is corrected while the attenuation value decreases.

### Claim 7 (depends on 1)

A method according to claim 1, wherein essentially constant attenuation is obtained from DC-26 GHz.

### Claim 8

An ultra-wideband attenuator with improved stability and reduced phase variations, with respect to temperature variations, comprising:
a) an attenuator implemented in π- topology consisting of:
a.1) a serial path between the input and the output of said attenuator, including a first serial resistor (Rs1) connected to said input, followed by a serial inductor (Ls), followed by a second serial resistor (Rs2) connected to said output;
a.2) a first transistor (T1) bridging between said input and said output, for controlling the impedance of said serial path by a first control input (Vc1) provided to said first transistor (T1);
a.3) a first parallel path between said input and ground, including a first parallel transistor (T2a) followed by first parallel resistor (Rp1);
a.4) a second parallel path between said output and ground, including a second parallel transistor (T2b) followed by second parallel resistor (Rp2);
a.5) a second control input (Vc2) commonly provided to first parallel transistor (T2a) and to said second parallel transistor (T2b), for controlling the impedance of said first and second parallel paths;
b) a common serial resistor (Rs) in said serial path being unification of said serial resistors and two serial inductors (Ls1) and (Ls2), being a division of said serial inductor (Ls), such that one serial inductor (Ls1) is connected between said input and a first contract of said common serial resistor (Rs) and the other serial inductor (Ls2) is connected between said output and the other contact of said common serial resistor (Rs);
c) a first resistor (Rp11) being smaller than (Rp1) connected to the input and a second smaller resistor (Rp12) being smaller than (Rp1) connected to said to first smaller resistor (Rp11) via said first parallel transistor (T2a) and to ground via a third parallel transistor (T3a);
d) a third resistor (Rp21) being smaller than (Rp2) connected to the input and a fourth smaller resistor (Rp22) being smaller than (Rp2) connected to said third smaller resistor (Rp21) via said first parallel transistor (T2b) and to ground via a third parallel transistor (T3b);
e) a first feedback capacitor (Cfb1) connected between the common point connecting between the ungrounded port of said second parallel transistor (T3a) and the first contract of said common serial resistor (Rs) and a second feedback capacitor (Cfb2) connecting between the common point connecting between the ungrounded port of said fourth parallel transistor (T3b) and the second contract of said common serial resistor (Rs);
f) a controller adapted to control said first and second parallel transistors (T2a and T2b) by said second control input (Vc2), to simultaneously control also said third and said fourth parallel transistors (T3a and T3b) by said second control input (Vc2), and to control said first and said second control inputs (Vc1 and Vc2) to obtain a desired attenuation between said input and output of said attenuator.

### Claim 9 (depends on 8)

An ultra-wideband attenuator according to claim 8, in which the transistors are implemented using MOSFET technology.

### Claim 10 (depends on 8)

An ultra-wideband attenuator according to claim 8, implemented using differential or single-ended topology.

### Claim 11 (depends on 8)

An ultra-wideband attenuator according to claim 8, in which the circuitry for implementing said attenuator is symmetrical, such that:
Rs1=Rs2;
Rp1=Rp2;
first smaller resistor=third smaller resistor;
second smaller resistor=fourth smaller resistor.

### Claim 12 (depends on 8)

An ultra-wideband attenuator according to claim 8, in which optimal performance is obtained when the resistors are split into two equal smaller resistors.

### Claim 13 (depends on 8)

An ultra-wideband attenuator according to claim 8, in which the phase imbalance is corrected while the attenuation value decreases.

### Claim 14 (depends on 8)

An ultra-wideband attenuator according to claim 8, in which essentially constant attenuation is obtained from DC-26 GHz.