# US 12,113,500 B2 · Attenuator circuit, receiver, base station, mobile device and method for operating an attenuator circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,500 B2 - Document ID: US12113500B2 - Status: Granted - Kind: B2 - Application number: 17/131,809 - Filed: 2020-12-23 - Published: 2022-06-23 - Granted: 2024-10-08 - Earliest claimed: 2020-12-23 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Daniel Gruber; L Mark Elzinga; Martin Clara; Giacomo Cascio - Web page: https://patentgrep.com/patent/US12113500B2 ## CPC - H03H 7/25: comprising an element controlled by an electric or magnetic variable (H03H7/27 takes precedence) - H03H 11/24: Frequency-independent attenuators - H03H 11/245: {using field-effect transistor} - H04B 1/1607: {Supply circuits (converters H02M; filters therefor H02M1/14; voltage stabilisers G05F1/46)} - H04W 88/08: Access point devices - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H04B: TRANSMISSION - H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72) ## Abstract An attenuator circuit is provided. The attenuator circuit includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair. Further, the attenuator circuit includes a first plurality of resistive elements coupled in series between the first input node and a first output node for outputting a first output signal. The attenuator circuit additionally includes a second plurality of resistive elements coupled in series between the second input node and a second output node for outputting a second output signal. In addition, the attenuator circuit includes a shunt path coupled to a first intermediate node and a second intermediate node. The first intermedia node is arranged between two resistive elements of the first plurality of resistive elements. The second intermedia node is arranged between two resistive elements of the second plurality of resistive elements. The shunt path comprises a switch circuit configured to selectively couple the first intermediate node and the second intermediate node based on one or more control signals. ## Claims ### Claim 1 An attenuator circuit, comprising: a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair; a first plurality of resistive elements coupled in series between the first input node and a first output node for outputting a first output signal; a second plurality of resistive elements coupled in series between the second input node and a second output node for outputting a second output signal; a first shunt path coupled to a first intermediate node and a second intermediate node, the first intermediate node being arranged between two resistive elements of the first plurality of resistive elements, the second intermediate node being arranged between two resistive elements of the second plurality of resistive elements, wherein the first shunt path comprises a first switch circuit configured to selectively couple the first intermediate node and the second intermediate node based on one or more first control signals; and a second shunt path coupled to a third intermediate node and a fourth intermediate node, the third intermediate node being arranged between two resistive elements of the first plurality of resistive elements, the fourth intermediate node being arranged between two resistive elements of the second plurality of resistive elements, and wherein the second shunt path comprises a second switch circuit configured to selectively couple the third intermediate node and the fourth intermediate node based on one or more second control signals. ### Claim 2 (depends on 1) The attenuator circuit of claim 1, wherein the first switch circuit and/or the second switch circuit is further configured to adjust its on-state resistance based on the one or more first control signals and/or the one or more second control signals, respectively. ### Claim 3 (depends on 1) The attenuator circuit of claim 1, wherein the first switch circuit and/or the second switch circuit comprises a plurality of switches coupled in parallel, and wherein each of the switches is configured to selectively couple the first intermediate node and the second intermediate node or the second intermediate node and the fourth intermediate node based on a respective first or second control signal. ### Claim 4 (depends on 3) The attenuator circuit of claim 3, wherein at least one of the plurality of switches comprises a semiconductor switch. ### Claim 5 (depends on 3) The attenuator circuit of claim 3, wherein at least one of the plurality of switches comprises a transmission gate. ### Claim 6 (depends on 5) The attenuator circuit of claim 5, wherein the transmission gate comprises: two transistors of different conductivity types which are coupled in parallel; and an inverter configured to generate an inverted control signal based on the respective first control signal for the first switch circuit or the respective second control signal for the second switch circuit, wherein a gate terminal of one of the two transistors is configured to receive the respective first control signal for the first switch circuit or the respective second control signal for the second switch circuit, and wherein a gate terminal of the other of the two transistors is configured to receive the inverted control signal. ### Claim 7 (depends on 6) The attenuator circuit of claim 6, wherein one or more respective resistors are coupled in series with the gate terminal of at least one of the two transistors. ### Claim 8 (depends on 3) The attenuator circuit of claim 3, wherein at least one of the plurality of switches comprises a plurality of stacked transistors, and wherein gate terminals of the plurality of stacked transistors are configured to receive the respective first control signal for the first switch circuit or the respective second control signal for the second switch circuit. ### Claim 9 (depends on 8) The attenuator circuit of claim 8, wherein one or more respective resistors are coupled in series with the gate terminal of at least one of the plurality of stacked transistors. ### Claim 10 (depends on 1) The attenuator circuit of claim 1, wherein a summed resistance of the resistive elements coupled between the first input node and the first intermediate node is equal to a summed resistance of the resistive elements coupled between the second input node and the second intermediate node, and wherein a summed resistance of the resistive elements coupled between the first intermediate node and the first output node is equal to a summed resistance of the resistive elements coupled between the second intermediate node and the second output node. ### Claim 11 (depends on 1) The attenuator circuit of claim 1, wherein the first intermediate node and the third intermediate node are arranged between different resistive elements of the first plurality of resistive elements, and wherein the second intermediate node and the fourth intermediate node are arranged between different resistive elements of the second plurality of resistive elements. ### Claim 12 (depends on 1) The attenuator circuit of claim 1, wherein the second switch circuit is further configured to adjust its on-state resistance based on the one or more second control signals. ### Claim 13 (depends on 1) The attenuator circuit of claim 1, wherein a summed resistance of the resistive elements coupled between the first input node and the third intermediate node is equal to a summed resistance of the resistive elements coupled between the second input node and the fourth intermediate node, and wherein a summed resistance of the resistive elements coupled between the third intermediate node and the first output node is equal to a summed resistance of the resistive elements coupled between the fourth intermediate node and the second output node. ### Claim 14 (depends on 1) The attenuator circuit of claim 1, wherein at least a part of the first plurality of resistive elements respectively is a single resistor. ### Claim 15 (depends on 1) The attenuator circuit of claim 1, wherein at least a part of the first plurality of resistive elements respectively comprises a plurality of resistors coupled in parallel. ### Claim 16 (depends on 1) A receiver comprising: an attenuator circuit according to claim 1; a load coupled to the first output node and the second output of the attenuator circuit for receiving the first output signal and the second output signal; and a control circuit configured to generate the one or more control signals for the first switch circuit and the second switch circuit based on a target attenuation of the first input signal and the second input signal. ### Claim 17 (depends on 16) The receiver of claim 16, wherein the first input signal and the second input signal are radio frequency signals. ### Claim 18 (depends on 16) The receiver of claim 16, further comprising analog circuitry configured to receive a radio frequency receive signal from an antenna element, and to supply the first input signal and the second input signal to the attenuator circuit based on the radio frequency receive signal. ### Claim 19 (depends on 16) The receiver of claim 16, wherein the first input signal and the second input signal are DC signals. ### Claim 20 (depends on 16) The receiver of claim 16, wherein the load comprises one or more amplifiers configured to fix the first output node and the second output of the attenuator circuit to a local virtual ground. ### Claim 21 (depends on 16) The receiver of claim 16, wherein the load is one or more input buffers of an analog-to-digital converter. ### Claim 22 (depends on 16) A base station, comprising: a receiver according to claim 16; and a transmitter configured to generate a radio frequency transmit signal. ### Claim 23 A method for operating an attenuator circuit, the method comprising: receiving a respective one of a first input signal and a second input signal forming a differential input signal pair at a first input node and a second input node of the attenuator circuit, wherein a first plurality of resistive elements is coupled in series between the first input node and a first output node for outputting a first output signal, wherein a second plurality of resistive elements is coupled in series between the second input node and a second output node for outputting a second output signal, wherein a first shunt path is coupled to a first intermediate node and a second intermediate node and a second shunt path is coupled to a third intermediate node and a fourth intermediate node, the first intermediate node being arranged between two resistive elements of the first plurality of resistive elements, the second intermediate node being arranged between two resistive elements of the second plurality of resistive elements, the third intermediate node being arranged between two resistive elements of the first plurality of resistive elements, the fourth intermediate node being arranged between two resistive elements of the second plurality of resistive elements; and supplying, based on a target attenuation of the first input signal and the second input signal, one or more first control signals to a first switch circuit of the first shunt path for controlling the first switch circuit to selectively couple the first intermediate node and the second intermediate node and one or more second control signals to a second switch circuit of the second shunt path for controlling the second switch circuit to selectively couple the third intermediate node and the fourth intermediate node. ### Claim 24 (depends on 23) The method of claim 23, wherein an on-state resistance of the first switch circuit and/or the second switch circuit is adjustable, and wherein the method further comprises: adjusting the on-state resistance of the first switch circuit and/or the second switch circuit to a target resistance using the one or more first control signals and/or the one or more second control signals, respectively, wherein the target resistance is selected based on the target attenuation of the first input signal and the second input signal.