# US 12,113,498 B2 · Signal processing circuits and devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,498 B2 - Document ID: US12113498B2 - Status: Granted - Kind: B2 - Application number: 18/181,575 - Filed: 2023-03-10 - Published: 2023-07-06 - Granted: 2024-10-08 - Earliest claimed: 2020-12-31 - Assignees: Shenzhen Shokz Co., Ltd. - Applicants: Shenzhen Shokz Co., Ltd. - Inventors: Xin Zhou; Lei Su; Yuxiang Zhang; Meiqi Li; Fengyun Liao; Xin Qi - Web page: https://patentgrep.com/patent/US12113498B2 ## CPC - A61B 5/304: Switching circuits - H03H 11/04: Frequency selective two-port networks - A61B 5/313: for electromyography [EMG] - A61B 5/7225: {Details of analogue processing, e.g. isolation amplifier, gain or sensitivity adjustment, filtering, baseline or drift compensation (input circuits for detecting, measuring, or recording bioelectric or biomagnetic signals A61B5/30; specific diagnostic methods using bioelectric or biomagnetic signals A61B5/316)} - A61B 5/725: {using specific filters therefor, e.g. Kalman or adaptive filters (specific diagnostics methods using using bioelectric or biomagnetic signals A61B5/316)} - A61B 5/0015: {characterised by features of the telemetry system} - A61B 5/305: Common mode rejection - A61B 5/6833: {Adhesive patches} - H03H 2011/0488: {Notch or bandstop filters} - A61B: DIAGNOSIS; SURGERY; IDENTIFICATION (usefulness limited to only animals A61D) - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) ## Abstract The embodiments of the present disclosure are for a signal processing circuit. The signal processing circuit includes an analog circuit. The analog circuit is used for processing an initial signal it receives. The initial signal includes a target signal and a noise signal. The analog circuit includes a first processing circuit and a second processing circuit. The first processing circuit is used to increase a ratio of the target signal to the noise signal, and output a first processed signal. The second processing circuit is used to amplify the first processed signal. A gain multiple of the second processing circuit to the first processed signal varies with a frequency of the first processed signal. The first processing circuit includes a common mode signal suppression circuit used to suppress a common mode signal in the initial signal, a low-pass filter circuit, and a high-pass filter circuit. ## Claims ### Claim 1 A signal processing circuit, comprising an analog circuit configured to process an initial signal received by the analog circuit, the initial signal comprising a target signal and a noise signal, wherein the analog circuit comprises: a first processing circuit, configured to increase a ratio of the target signal to the noise signal and output a first processed signal; and a second processing circuit connected to the first processing circuit, configured to amplify the first processed signal, wherein a gain multiple of the second processing circuit to the first processed signal varies with a frequency of the first processed signal, wherein: the first processing circuit includes a common mode signal suppression circuit, a low-pass filter circuit, and a high-pass filter circuit, the common mode signal suppression circuit is configured to suppress a common mode signal in the initial signal. ### Claim 2 (depends on 1) The signal processing circuit of claim 1, wherein the common mode signal suppression circuit comprises a differential amplifier. ### Claim 3 (depends on 2) The signal processing circuit of claim 2, wherein the low-pass filter circuit includes a bridge circuit structure formed at an input end of the differential amplifier. ### Claim 4 (depends on 2) The signal processing circuit of claim 2, wherein an input impedance of the differential amplifier is greater than 10 MΩ. ### Claim 5 (depends on 1) The signal processing circuit of claim 1, wherein an upper cut-off frequency point of the low-pass filter circuit is within a frequency range of 100 Hz-1000 Hz. ### Claim 6 (depends on 1) The signal processing circuit of claim 1, wherein a lower cut-off frequency point of the high-pass filter circuit is within a frequency range of 5 Hz-200 Hz. ### Claim 7 (depends on 1) The signal processing circuit of claim 1, wherein the first processing circuit comprises a notch circuit for suppressing a power frequency signal. ### Claim 8 (depends on 7) The signal processing circuit of claim 7, wherein the notch circuit comprises a cascaded notch circuit, and the cascaded notch circuit is also configured to suppress one or more harmonics in the power frequency signal. ### Claim 9 (depends on 7) The signal processing circuit of claim 7, wherein the notch circuit comprises a dual-T active notch circuit. ### Claim 10 (depends on 1) The signal processing circuit of claim 1, wherein the first processing circuit further comprises a voltage-controlled low-pass filter circuit, and the voltage-controlled low-pass filter circuit is configured to provide a gain near a target frequency of the voltage-controlled low-pass filter circuit and is combined with the low-pass filter circuit to compensate an attenuation of the low-pass filter circuit. ### Claim 11 (depends on 1) The signal processing circuit of claim 1, wherein the increasing the ratio of the target signal to the noise signal by the first processing circuit comprises: performing amplification processing of a first amplification factor on the target signal; and performing attenuation processing on the noise signal. ### Claim 12 (depends on 11) The signal processing circuit of claim 11, wherein the second processing circuit comprises an amplifier circuit, a feedback circuit, and a follower, the amplifier circuit is configured to amplify the first processed signal by a second amplification factor, the second amplification factor being greater than the first amplification factor, and the follower is configured to isolate an influence of an output end of the signal processing circuit. ### Claim 13 (depends on 1) The signal processing circuit of claim 1, wherein the second processing circuit has a greater gain response to the first processed signal in a first frequency range than that of a frequency range outside the first frequency range. ### Claim 14 (depends on 13) The signal processing circuit of claim 13, wherein the first frequency range includes 20 Hz-140 Hz. ### Claim 15 (depends on 1) The signal processing circuit of claim 1, wherein the initial signal comprises a myoelectric signal. ### Claim 16 (depends on 1) The signal processing circuit of claim 1, further comprising: a control circuit, a switch circuit, and at least two signal acquisition circuits, wherein, the at least two signal acquisition circuits are configured to acquire at least two initial signals; the switch circuit is configured to control a conduction between the at least two signal acquisition circuits and the analog circuit, so that initial signals acquired by a part of the at least two signal acquisition circuits are transmitted to the analog circuit at the same time; and the control circuit is configured to receive the target signal processed by the analog circuit, and sample the processed target signal. ### Claim 17 (depends on 16) The signal processing circuit of claim 16, wherein the switch circuit includes a plurality of input channels, each signal acquisition circuit in the at least two signal acquisition circuits is independently connected to one input channel, and the switch circuit selects only one input channel to be conducted at the same time based on a control signal of the control circuit. ### Claim 18 A signal processing device, comprising: a signal processing circuit the signal processing circuit comprising an analog circuit configured to process an initial signal received by the analog circuit, the initial signal comprising a target signal and a noise signal, wherein the analog circuit comprises: a first processing circuit, configured to increase a ratio of the target signal to the noise signal and output a first Processed signal; and a second processing circuit connected to the first processing circuit, configured to amplify the first processed signal, wherein a gain multiple of the second processing circuit to the first processed signal varies with a frequency of the first processed signal, wherein: the first processing circuit includes a common mode signal suppression circuit, a low-pass filter circuit, and a high-pass filter circuit, the common mode signal suppression circuit is configured to suppress a common mode signal in the initial signal. ### Claim 19 (depends on 18) The signal processing device of claim 18, wherein the common mode signal suppression circuit comprises a differential amplifier. ### Claim 20 (depends on 19) The signal processing device of claim 19, wherein the low-pass filter circuit includes a bridge circuit structure formed at an input end of the differential amplifier.