US 12,113,494 B2Granted

Differential amplifier circuit, reception circuit, and semiconductor integrated circuit

AssigneeSocionext Inc.

InventorsTakuya Fujimura, Hideki Kano

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Abstract

In a differential amplifier circuit, a differential amplifier circuit unit includes: first and second transistors provided between a current source circuit and a load circuit, which receives differential input signals at gates to generate differential output signals at drains; and a third transistor connected between sources of the first and second transistors, which receives a control signal at a gate. A replica amplifier circuit unit includes: a voltage generation circuit which generates first and second reference voltages; first and second replica transistors which receives the first and second reference voltages at gates to generate replica output signals at drains; a third replica transistor connected between sources of the first and second replica transistors, which receives the control signal at a gate; and an operational amplifier which generates the control signal according to a difference between at least one of the first and second reference voltages and the replica output signal.

Claims20

Dependent claims

A differential amplifier circuit, comprising:

a differential amplifier circuit unit;
and
a replica amplifier circuit unit, wherein:
the differential amplifier circuit unit includes:
first and second transistors provided between a current source circuit and a load circuit, and configured to receive differential input signals at gates thereof to generate differential output signals at drains thereof;
and
a third transistor connected between sources of the first and second transistors, and configured to receive a control signal at a gate thereof;
and
the replica amplifier circuit unit includes:
a voltage generation circuit configured to generate first and second reference voltages;
first and second replica transistors being replicas of the first and second transistors, the first and second replica transistors being configured to receive the first and second reference voltages at gates thereof to generate replica output signals at drains thereof;
a third replica transistor connected between sources of the first and second replica transistors, and configured to receive the control signal, at a gate thereof;
and
an operational amplifier configured to generate the control signal in accordance with a difference between at least one of the first and second reference voltages and the replica output signal, wherein
the operational amplifier is configured to generate the control signal so that a gain of the replica amplifier circuit unit is constant.

12 more elements

A reception circuit, comprising:

a continuous time linear equalizer;
a decision feedback equalizer configured to receive an output signal of the continuous time linear equalizer;
a clock generator configured to output a clock signal to the decision feedback equalizer;
and
a demultiplexer configured to receive an output signal of the decision feedback equalizer, wherein
the continuous time linear equalizer includes a differential amplifier circuit, wherein
the differential amplifier circuit includes:
a differential amplifier circuit unit;
and
a replica amplifier circuit unit, wherein:
the differential amplifier circuit unit includes:
first and second transistors provided between a current source circuit and a load circuit, and configured to receive differential input signals at gates thereof to generate differential output signals at drains thereof;
and
a third transistor connected between sources of the first and second transistors, and configured to receive a control signal at a gate thereof;
and
the replica amplifier circuit unit includes:
a voltage generation circuit configured to generate first and second reference voltages;
first and second replica transistors being replicas of the first and second transistors, the first and second replica transistors being configured to receive the first and second reference voltages at gates thereof to generate replica output signals at drains thereof;
a third replica transistor connected between sources of the first and second replica transistors, and configured to receive the control signal at a gate thereof;
and
an operational amplifier configured to generate the control signal in accordance with a difference between at least one of the first and second reference voltages and the replica output signal, wherein
the operational amplifier is configured to generate the control signal so that a gain of the replica amplifier circuit unit is constant.

19 more elements

A semiconductor integrated circuit, comprising:

a reception circuit;
and
an internal circuit configured to process an output signal of the reception circuit, wherein
the reception circuit includes:
a continuous time linear equalizer;
a decision feedback equalizer configured to receive an output signal of the continuous time linear equalizer;
a clock generator configured to output a clock signal to the decision feedback equalizer;
and
a demultiplexer configured to receive an output signal of the decision feedback equalizer, wherein
the continuous time linear equalizer includes a differential amplifier circuit, wherein
the differential amplifier circuit includes:
a differential amplifier circuit unit;
and
a replica amplifier circuit unit, wherein:
the differential amplifier circuit unit includes:
first and second transistors provided between a current source circuit and a load circuit, and configured to receive differential input signals at gates thereof to generate differential output signals at drains thereof;
and
a third transistor connected between sources of the first and second transistors, and configured to receive a control signal at a gate thereof;
and
the replica amplifier circuit unit includes:
a voltage generation circuit configured to generate first and second reference voltages;
first and second replica transistors being replicas of the first and second transistors, and the first and second replica transistors being configured to receive the first and second reference voltages at gates thereof to generate replica output signals at drains thereof;
a third replica transistor connected between sources of the first and second replica transistors, and configured to receive the control signal at a gate;
and
an operational amplifier configured to generate the control signal in accordance with a difference between at least one of the first and second reference voltages and the replica output signal, wherein
the operational amplifier is configured to generate the control signal so that a gain of the replica amplifier circuit unit is constant.

23 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/836,709Filed 9 Jun 2022 · continuation
Priority: 17 Dec 2019
Published: US 2022/0302889 A122 Sep 2022
Granted: 8 Oct 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H03F 3/45179
Characterised by the way of implementation of the active amplifying circuit in the differential amplifier: using MOSFET transistors as the active…
H03F 1/301
Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters: in MOSFET amplifiers
H03F 3/195
With semiconductor devices only: in integrated circuits
H03F 3/45201
Pl types: non-folded cascode stages