# US 12,113,491 B2 · Active splitting amplifier circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,491 B2 - Document ID: US12113491B2 - Status: Granted - Kind: B2 - Application number: 17/478,746 - Filed: 2021-09-17 - Published: 2022-03-24 - Granted: 2024-10-08 - Earliest claimed: 2020-09-23 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Alaaeldien Mohamed Abdelrazek Medra; Xingyi Hua; Naushad Dhamani; Francesco Gatta - Web page: https://patentgrep.com/patent/US12113491B2 ## CPC - H03F 3/19: with semiconductor devices only - H03F 3/193: with field-effect devices (H03F3/195 takes precedence) - H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)} - H04B 1/16: Circuits - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F: AMPLIFIERS - H04B: TRANSMISSION ## Abstract Aspects of the present disclosure relate to a receiver including an amplifier circuit. The amplifier circuit includes a common-source amplifier having an input and an output, and a common-gate amplifier having an input and an output, wherein the input of the common-gate amplifier is coupled to the output of the common-source amplifier. The receiver also includes a first receive chain coupled to the output of the common-gate amplifier, and a second receive chain coupled to the output of the common-source amplifier. ## Claims ### Claim 1 A receiver, comprising: an amplifier circuit, wherein the amplifier circuit includes: a first common-source amplifier having an input and an output, the first common-source amplifier comprising: a first transistor having a source, a gate, and a drain, wherein the gate of the first transistor is coupled to the input of the first common-source amplifier, and the drain of the first transistor is coupled to the output of the first common-source amplifier; a source-degeneration inductor coupled between the source of the first transistor and a ground; and a gate inductor coupled between the input of the first common-source amplifier and the gate of the first transistor; and a first common-gate amplifier having an input and an output, wherein the input of the first common-gate amplifier is coupled to the output of the first common-source amplifier; a first receive chain coupled to the output of the first common-gate amplifier; and a second receive chain coupled to the output of the first common-source amplifier. ### Claim 2 (depends on 1) The receiver of claim 1, further comprising an antenna coupled to the input of the first common-source amplifier. ### Claim 3 (depends on 1) The receiver of claim 1, wherein the first receive chain comprises a first mixer coupled to the output of the first common-gate amplifier, and the second receive chain comprises a second mixer coupled to the output of the first common-source amplifier. ### Claim 4 (depends on 3) The receiver of claim 3, wherein the first receive chain further comprises a first filter coupled between the first mixer and a baseband processor, and the second receive chain further comprises a second filter coupled between the second mixer and the baseband processor. ### Claim 5 (depends on 1) The receiver of claim 1, wherein the first common-gate amplifier comprises: a second transistor having a source, a gate, and a drain, wherein the source of the second transistor is coupled to the input of the first common-gate amplifier, and the gate of the second transistor is coupled to a bias circuit; and a load coupled to the drain of the second transistor. ### Claim 6 (depends on 5) The receiver of claim 5, wherein the load comprises a load inductor, and the output of the first common-gate amplifier is coupled to the load inductor. ### Claim 7 (depends on 5) The receiver of claim 5, further comprising a bias circuit, wherein the gate of the first transistor is coupled to the bias circuit via a first resistor and the gate of the second transistor is coupled to the bias circuit via a second resistor. ### Claim 8 A receiver, comprising: an amplifier circuit, wherein the amplifier circuit includes: a first common-source amplifier having an input and an output; and a first common-gate amplifier having an input and an output, wherein the input of the first common-gate amplifier is coupled to the output of the first common-source amplifier; a first switch circuit having a first input, a second input, and an output, wherein the first input of the first switch circuit is coupled to the output of the first common-gate amplifier, and the second input of the first switch circuit is coupled to the output of the first common-source amplifier; a second switch circuit having a first input, a second input, and an output, wherein the first input of the second switch circuit is coupled to the output of the first common-gate amplifier, and the second input of the second switch circuit is coupled to the output of the first common-source amplifier; and an attenuator, wherein the attenuator is coupled between the output of the first common-source amplifier and the first input of the first switch circuit, and the attenuator is coupled between the output of the first common-source amplifier and the first input of the second switch circuit. ### Claim 9 (depends on 1) The receiver of claim 1, wherein the amplifier circuit further comprises: a second common-source amplifier having an input and an output, wherein the input of the second common-source amplifier is coupled to the input of the first common-source amplifier; and a second common-gate amplifier having an input and an output, wherein the input of the second common-gate amplifier is coupled to the output of the second common-source amplifier, and the output of the second common-gate amplifier is coupled to the output of the first common-gate amplifier. ### Claim 10 A receiver, comprising: an amplifier circuit, wherein the amplifier circuit includes: a first common-source amplifier having an input and an output; and a first common-gate amplifier having an input and an output, wherein the input of the first common-gate amplifier is coupled to the output of the first common-source amplifier; a first switch circuit having a first input, a second input, and an output, wherein the first input of the first switch circuit is coupled to the output of the first common-gate amplifier, and the second input of the first switch circuit is coupled to the output of the first common-source amplifier; a second switch circuit having a first input, a second input, and an output, wherein the first input of the second switch circuit is coupled to the output of the first common-gate amplifier, and the second input of the second switch circuit is coupled to the output of the first common-source amplifier; and a splitter having an input, a first output, and a second output, wherein the input of the splitter is coupled to the output of the first common-gate amplifier, the first output of the splitter is coupled to a third input of the first switch circuit, and the second output of the splitter is coupled to a third input of the second switch circuit. ### Claim 11 (depends on 10) The receiver of claim 10, further comprising: a first receive chain coupled to the output of the first switch circuit, the first receive chain comprising a first mixer; and a second receive chain coupled to the output of the second switch circuit, the second receive chain comprising a second mixer. ### Claim 12 (depends on 11) The receiver of claim 11, wherein the first receive chain further comprises a first filter coupled between the first mixer and a baseband processor, and the second receive chain further comprises a second filter coupled between the second mixer and the baseband processor. ### Claim 13 (depends on 10) The receiver of claim 10, further comprising a controller coupled to the first switch circuit and the second switch circuit, wherein the controller is configured to: in a first mode, cause the first switch circuit to couple the first input of the first switch circuit to the output of the first switch circuit, and cause the second switch circuit to couple the second input of the second switch circuit to the output of the second switch circuit; and in a second mode, cause the first switch circuit to couple the second input of the first switch circuit to the output of the first switch circuit, and cause the second switch circuit to couple the first input of the second switch circuit to the output of the second switch circuit. ### Claim 14 (depends on 10) The receiver of claim 10, wherein the first switch circuit comprises a first attenuator, and the second switch circuit comprises a second attenuator. ### Claim 15 (depends on 10) The receiver of claim 10, further comprising an attenuator, wherein the attenuator is coupled between the output of the first common-source amplifier and the first input of the first switch circuit, and the attenuator is coupled between the output of the first common-source amplifier and the first input of the second switch circuit. ### Claim 16 (depends on 15) The receiver of claim 15, wherein the attenuator comprises a variable resistor. ### Claim 17 (depends on 10) The receiver of claim 10, wherein: the first common-source amplifier comprises: a first transistor having a source, a gate, and a drain, wherein the gate of the first transistor is coupled to the input of the first common-source amplifier, and the drain of the first transistor is coupled to the output of the first common-source amplifier; and a source-degeneration inductor coupled between the source of the first transistor and a ground; and the first common-gate amplifier comprises: a second transistor having a source, a gate, and a drain, wherein the source of the second transistor is coupled to the input of the first common-gate amplifier, and the gate of the second transistor is coupled to a bias circuit; and a load coupled to the drain of the second transistor. ### Claim 18 (depends on 17) The receiver of claim 17, wherein the load comprises a load inductor, and the output of the first common-gate amplifier is coupled to the load inductor. ### Claim 19 (depends on 10) The receiver of claim 10, wherein the amplifier circuit further comprises: a second common-source amplifier having an input and an output, wherein the input of the second common-source amplifier is coupled to the input of the first common-source amplifier; and a second common-gate amplifier having an input and an output, wherein the input of the second common-gate amplifier is coupled to the output of the second common-source amplifier, and the output of the second common-gate amplifier is coupled to the output of the first common-gate amplifier. ### Claim 20 A method for wireless communications, comprising: receiving multiple signals via an antenna; passing the multiple signals through a first gain path, the first gain path including a common-source amplifier and a common-gate amplifier; passing the multiple signals through a second gain path, the second gain path including the common-source amplifier and excluding the common-gate amplifier; in a first mode, routing the multiple signals passing through the first gain path to a first receive chain and routing the multiple signals passing through the second gain path to a second receive chain; in a second mode, routing the multiple signals passing through the first gain path to the second receive chain and routing the multiple signals passing through the second gain path to the first receive chain; in a third mode, splitting the multiple signals passing through the first gain path into a first split signal and a second split signal; attenuating the first split signal by a first attenuation; and attenuating the second split signal by a second attenuation, wherein the second attenuation is different from the first attenuation. ### Claim 21 (depends on 20) The method of claim 20, wherein the second gain path includes an attenuator. ### Claim 22 (depends on 21) The method of claim 21, wherein the first gain path excludes the attenuator. ### Claim 23 (depends on 20) The method of claim 20, further comprising: mixing the multiple signals passing through the first gain path with a first oscillator signal; and mixing the multiple signals passing through the second gain path with a second oscillator signal, wherein the first oscillator signal and the second oscillator signal have different frequencies. ### Claim 24 A receiver, comprising: an amplifier circuit, wherein the amplifier circuit includes: a first transistor having a source, a gate, and a drain; a second transistor having a source, a gate, and a drain, wherein the source of the second transistor is coupled to the drain of the first transistor, and the gate of the second transistor is coupled to a bias circuit; a third transistor having a source, a gate, and a drain; a fourth transistor having a source, a gate, and a drain, wherein the source of the fourth transistor is coupled to the drain of the third transistor, and the gate of the fourth transistor is coupled to the bias circuit; a load coupled to the drain of the second transistor and the drain of the fourth transistor; wherein an input of the amplifier circuit is coupled to the gate of the first transistor and the gate of the third transistor, a first output of the amplifier circuit is coupled to the load, and a second output of the amplifier circuit is coupled between the drain of the first transistor and the source of the second transistor; a first switch circuit having a first input, a second input, and an output, wherein the first input of the first switch circuit is coupled to the first output of the amplifier circuit, and the second input of the first switch circuit is coupled to the second output of the amplifier circuit; and a second switch circuit having a first input, a second input, and an output, wherein the first input of the second switch circuit is coupled to the first output of the amplifier circuit, and the second input of the second switch circuit is coupled to the second output of the amplifier circuit; and a splitter having an input, a first output, and a second output, wherein the input of the splitter is coupled to the load, the first output of the splitter is coupled to a third input of the first switch circuit, and the second output of the splitter is coupled to a third input of the second switch circuit. ### Claim 25 (depends on 24) The receiver of claim 24, further comprising a controller coupled to the first switch circuit and the second switch circuit, wherein the controller is configured to: in a first mode, cause the first switch circuit to couple the first input of the first switch circuit to the output of the first switch circuit, and cause the second switch circuit to couple the second input of the second switch circuit to the output of the second switch circuit; and in a second mode, cause the first switch circuit to couple the second input of the first switch circuit to the output of the first switch circuit, and cause the second switch circuit to couple the first input of the second switch circuit to the output of the second switch circuit.