# US 12,113,481 B2 · Switch circuit, mixer, and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,481 B2 - Document ID: US12113481B2 - Status: Granted - Kind: B2 - Application number: 17/514,564 - Filed: 2021-10-29 - Published: 2022-02-17 - Granted: 2024-10-08 - Earliest claimed: 2019-04-30 - Assignees: Huawei Technologies Co., Ltd. - Applicants: Huawei Technologies Co., Ltd. - Inventors: Yongli Zhou; Xiangju Jin; Yan Lai - Web page: https://patentgrep.com/patent/US12113481B2 ## CPC - H03D 7/1441: {using field-effect transistors (H03D7/145 takes precedence)} - H03D 7/1458: {Double balanced arrangements, i.e. where both input signals are differential} - H03D 7/1466: {Passive mixer arrangements} - H03D 7/1491: {Arrangements to linearise a transconductance stage of a mixer arrangement} - H10D 84/80: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) - H10D 89/10: Integrated device layouts - H10W 72/071: {Connecting or disconnecting} - H03D 2200/0088: Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products - H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A switch circuit, a mixer, and an electronic device, where the switch circuit includes a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, both a gate of the first MOS transistor and a gate of the fourth MOS transistor are connected to a first port, and both a gate of the second MOS transistor and a gate of the third MOS transistor are connected to a second port; and a lead between the gate of the first MOS transistor and the first port, a lead between the gate of the second MOS transistor and the second port, a lead between the gate of the third MOS transistor and the second port, and a lead between the gate of the fourth MOS transistor and the first port all have an equal length. In this way, linearity is relatively high. ## Claims ### Claim 1 A switch circuit, comprising: multiple transistors including a first metal-oxide-semiconductor (MOS) transistor having a first gate, a second MOS transistor having a second gate, a third MOS transistor having a third gate, and a fourth MOS transistor having a fourth gate, wherein the first MOS transistor and the third MOS transistor are symmetrically aligned along a first symmetry axis, wherein the second MOS transistor and the fourth MOS transistor are symmetrically aligned along the first symmetry axis, wherein the first MOS transistor and the second MOS transistor are symmetrically aligned forward and backward along a second symmetry axis, wherein the third MOS transistor and the fourth MOS transistor are symmetrically aligned forward and backward along the second symmetry axis, and wherein the first symmetry axis and the second symmetry axis are perpendicular to each other; a first port connected to both the first gate and the fourth gate; a second port connected to the second gate and the third gate; a first lead between the first gate and the first port; a second lead between the second gate and the second port; a third lead between the third gate and the second port; a fourth lead between the fourth gate and the first port, wherein the first lead, the second lead, the third lead, and the fourth lead all have an equal length; a first direct lead between the first gate and the fourth gate passing through a first position; a second direct lead between the second gate and the third gate passing through a second position, wherein the first position and the second position are same positions at different layers in the switch circuit, and wherein leads from the first gate to the first position, from the second gate to the second position, from the third gate to the second position, and from the fourth gate to the first position have an equal length; a fifth lead comprising: a first end connected to a third position of the first direct lead; a second end connected to the first port; a first part located on a first side of the first symmetry axis; and a second part located on a second side of the first symmetry axis, wherein the first side is opposite the second side of the first symmetry axis, and wherein the fifth lead passes through a fifth position, a sixth lead comprising: a third end connected to a fourth position of the second direct lead; a fourth end connected to the second port, wherein the third position and the fourth position are symmetrical along the first symmetry axis, and wherein the switch circuit is symmetrical along the first symmetry axis; a third part located on the first side of the first symmetry axis; and a fourth part located on the second side of the first symmetry axis, wherein the sixth lead passes through a sixth position, and wherein the fifth position and the sixth position are same positions at different layers in the switch circuit. ### Claim 2 (depends on 1) The switch circuit according to claim 1, wherein the first gate and the fourth gate are directly connected to form the first lead, wherein the second gate and the third gate are directly connected to form the second lead, and wherein both the first lead and the second lead are straight lines. ### Claim 3 (depends on 1) The switch circuit according to claim 1, wherein the first part of the fifth lead and a fifth part of the second direct lead are located in same positions at different layers in the switch circuit, wherein the second part of the fifth lead is parallel to the first symmetry axis, wherein a ninth part of the fifth lead is located on two sides of the first symmetry axis, wherein a tenth part of the fifth lead is parallel to the first symmetry axis, wherein the third part of the sixth lead and a sixth part of the first direct lead are located in same positions at different layers in the switch circuit, wherein the fourth part of the sixth lead is parallel to the first symmetry axis, wherein seventh part of the sixth lead is located on the two sides of the first symmetry axis, wherein than eighth part of the sixth lead is parallel to the first symmetry axis, wherein the third part of the fifth lead passes through the fifth position, and wherein the seventh part of the sixth lead passes through the sixth position. ### Claim 4 (depends on 1) The switch circuit according to claim 1, wherein the fifth lead is located on the first of the first symmetry axis and the sixth lead is located on the second side of the first symmetry axis, wherein the first part of the fifth lead and a fifth part of the second direct lead are located in same positions at different layers in the switch circuit, wherein the second part of the fifth lead is parallel to the first symmetry axis, wherein the third part of the sixth lead and a sixth part of the first direct lead are located in same positions at different layers in the switch circuit, and wherein the fourth part of the sixth lead is parallel to the first symmetry axis. ### Claim 5 (depends on 1) The switch circuit according to claim 1, wherein the third position and the first position are same positions, and wherein the fourth position and the second position are same positions. ### Claim 6 A mixer, comprising: a switch circuit including: multiple transistors including a first metal-oxide-semiconductor (MOS) transistor having a first gate, a second MOS transistor having a second gate, a third MOS transistor having a third gate, and a fourth MOS transistor having a fourth gate, wherein the first MOS transistor and the third MOS transistor are symmetrically aligned along a first symmetry axis, wherein the second MOS transistor and the fourth MOS transistor are symmetrically aligned along the first symmetry axis, wherein the first MOS transistor and the second MOS transistor are symmetrically aligned forward and backward along a second symmetry axis, wherein the third MOS transistor and the fourth MOS transistor are symmetrically aligned forward and backward along the second symmetry axis, and wherein the first symmetry axis and the second symmetry axis are perpendicular to each other; a first port connected to both the first gate and the fourth gate; a second port connected to the second gate and the third gate; a first lead between the first gate of the first MOS transistor and the first port; a second lead between the second gate of the second MOS transistor and the second port; a third lead between the third gate of the third MOS transistor and the second port; a fourth lead between the fourth gate of the fourth MOS transistor and the first port, wherein the first lead, the second lead, the third lead, and the fourth lead all have an equal length; a first direct lead between the first gate and the fourth gate passing through a first position; a second direct lead between the second gate and the third gate passing through a second position, wherein the first position and the second position are same positions at different layers in the switch circuit, and wherein leads from the first gate to the first position, from the second gate to the second position, from the third gate to the second position, and from the fourth gate to the first position have an equal length; a fifth lead comprising: a first end connected to a third position of the first direct lead; a second end connected to the first port; a first part located on a first side of the first symmetry axis; and a second part located on a second side of the first symmetry axis, wherein the first side is opposite the second side of the first symmetry axis, and wherein the fifth lead passes through a fifth position, a sixth lead comprising: a third end connected to a fourth position of the second direct lead; a fourth end connected to the second port, wherein the third position and the fourth position are symmetrical along the first symmetry axis, and wherein the switch circuit is symmetrical along the first symmetry axis; a third part located on the first side of the first symmetry axis; and a fourth part located on the second side of the first symmetry axis, wherein the sixth lead passes through a sixth position, and wherein the fifth position and the sixth position are same positions at different layers in the switch circuit. ### Claim 7 (depends on 6) The mixer according to claim 6, wherein the first port and the second port are both local oscillator ports for receiving a drive voltage, wherein a first source of the first MOS transistor and a second source of the second MOS transistor are both connected to a first input port, wherein a third source of the third MOS transistor and a fourth source of the fourth MOS transistor are both connected to a second input port, wherein a first drain of the first MOS transistor and a third drain of the third MOS transistor are both connected to a first output port, and wherein a second drain of the second MOS transistor and a fourth drain of the fourth MOS transistor are connected to a second output port. ### Claim 8 (depends on 7) The mixer according to claim 7, further comprising: a low-noise amplifier connected to both the first input port and the second input port; and a transimpedance amplifier connected to both the first output port and the second output port. ### Claim 9 A mixer, comprising: a first metal-oxide-semiconductor (MOS) transistor group including a circuit structure, a first MOS transistor having a first gate, a second MOS transistor having a second gate, a third MOS transistor having a third gate, and a fourth MOS transistor having a fourth gate, wherein the first MOS transistor and the third MOS transistor are symmetrically aligned along a first symmetry axis, wherein the second MOS transistor and the fourth MOS transistor are symmetrically aligned along the first symmetry axis, wherein the first MOS transistor and the second MOS transistor are symmetrically aligned forward and backward along a second symmetry axis, wherein the third MOS transistor and the fourth MOS transistor are symmetrically aligned forward and backward along the second symmetry axis, and wherein the first symmetry axis and the second symmetry axis are perpendicular to each other; a second MOS transistor group including a same circuit structure as the circuit structure of the first MOS transistor group, wherein the first MOS transistor group and the second MOS transistor group are symmetrically aligned along a reference symmetry axis; a first local oscillator port connected to the first gate and the fourth gate; a second local oscillator port connected to the second gate and the third gate; and a first lead between the first gate and the first local oscillator port; a second lead between the second gate and the second local oscillator port; a third lead between the third gate and the second local oscillator port; and a fourth lead between the fourth gate and the first local oscillator port, wherein the first lead, the second lead, the third lead, and the fourth lead all have an equal length; a first direct lead between the first gate and the fourth gate passing through a first position; a second direct lead between the second gate and the third gate passing through a second position, wherein the first position and the second position are same positions at different layers in the mixer, and wherein leads from the first gate to the first position, from the second gate to the second position, from the third gate to the second position, and from the fourth gate to the first position have an equal length; a fifth lead comprising: a first end connected to a third position of the first direct lead; a second end connected to the first local oscillator port; a first part located on a first side of the first symmetry axis; and a second part located on a second side of the first symmetry axis, wherein the first side is opposite the second side of the first symmetry axis, and wherein the fifth lead passes through a fifth position, a sixth lead comprising: a third end connected to a fourth position of the second direct lead; a fourth end connected to the second local oscillator port, wherein the third position and the fourth position are symmetrical along the first symmetry axis, and wherein the mixer is symmetrical along the first symmetry axis; a third part located on the first side of the first symmetry axis; and a fourth part located on the second side of the first symmetry axis, wherein the sixth lead passes through a sixth position, and wherein the fifth position and the sixth position are same positions at different layers in the mixer. ### Claim 10 (depends on 9) The mixer according to claim 9, wherein the first MOS transistor group and the second MOS transistor group are disposed on different deep N-wells. ### Claim 11 (depends on 9) The mixer according to claim 9, further comprising a low-noise amplifier connected to both a first input port and a second input port. ### Claim 12 (depends on 11) The mixer according to claim 11, further comprising a transimpedance amplifier connected to both a first output port and a second output port. ### Claim 13 (depends on 9) The mixer according to claim 9, wherein at least one of the first local oscillator port or the second local oscillator port is for receiving a drive voltage. ### Claim 14 (depends on 9) The mixer according to claim 9, wherein the first gate and the fourth gate are directly connected to form the first lead, and wherein the second gate and the third gate are directly connected to form the second lead. ### Claim 15 An electronic device, comprising: a mixer including: a first metal-oxide-semiconductor (MOS) transistor group including a circuit structure, a first MOS transistor having a first gate, a second MOS transistor having a second gate, a third MOS transistor having a third gate, and a fourth MOS transistor having a fourth gate, wherein the first MOS transistor and the third MOS transistor are symmetrically aligned along a first symmetry axis, wherein the second MOS transistor and the fourth MOS transistor are symmetrically aligned along the first symmetry axis, wherein the first MOS transistor and the second MOS transistor are symmetrically aligned forward and backward along a second symmetry axis, wherein the third MOS transistor and the fourth MOS transistor are symmetrically aligned forward and backward along the second symmetry axis, and wherein the first symmetry axis and the second symmetry axis are perpendicular to each other; a second MOS transistor group including a same circuit structure as the circuit structure of the first MOS transistor group, wherein the first MOS transistor group and the second MOS transistor group are symmetrically aligned along a reference symmetry axis; a first local oscillator port connected to both the first gate and the fourth gate; a second local oscillator port connected to both the second gate and the third gate; a first lead between the first gate and the first local oscillator port; a second lead between the second gate and the second local oscillator port; a third lead between the third gate and the second local oscillator port; a fourth lead between the fourth gate and the first local oscillator port, wherein the first lead, the second lead, the third lead, and the fourth lead all have an equal length; a first direct lead between the first gate and the fourth gate passing through a first position; a second direct lead between the second gate and the third gate passing through a second position, wherein the first position and the second position are same positions at different layers in the mixer, and wherein leads from the first gate to the first position, from the second gate to the second position, from the third gate to the second position, and from the fourth gate to the first position have an equal length; a fifth lead comprising: a first end connected to a third position of the first direct lead; a second end connected to the first local oscillator port; a first part located on a first side of the first symmetry axis; and a second part located on a second side of the first symmetry axis, wherein the first side is opposite the second side of the first symmetry axis, and wherein the fifth lead passes through a fifth position, a sixth lead comprising: a third end connected to a fourth position of the second direct lead; a fourth end connected to the second local oscillator port, wherein the third position and the fourth position are symmetrical along the first symmetry axis, and wherein the mixer is symmetrical along the first symmetry axis; a third part located on the first side of the first symmetry axis; and a fourth part located on the second side of the first symmetry axis, wherein the sixth lead passes through a sixth position, and wherein the fifth position and the sixth position are same positions at different layers in the mixer. ### Claim 16 (depends on 15) The electronic device according to claim 15, wherein the first MOS transistor group and the second MOS transistor group are disposed on different deep N-wells. ### Claim 17 (depends on 15) The electronic device according to claim 15, further comprising a low-noise amplifier connected to both a first input port and a second input port. ### Claim 18 (depends on 17) The electronic device according to claim 17, further comprising a transimpedance amplifier connected to both a first output port and a second output port. ### Claim 19 (depends on 15) The electronic device according to claim 15, wherein at least one of the first local oscillator port or the second local oscillator port is for receiving a drive voltage. ### Claim 20 (depends on 15) The electronic device according to claim 15, wherein the first gate and the fourth gate are directly connected to form the first lead, and wherein the second gate and the third gate are directly connected to form the second lead.