# US 12,113,301 B2 · Tile-based phased-array architecture for multi-band phased-array design and communication method

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- Number: US 12,113,301 B2
- Document ID: US12113301B2
- Status: Granted
- Kind: B2
- Application number: 17/235,415
- Filed: 2021-04-20
- Published: 2022-08-04
- Granted: 2024-10-08
- Earliest claimed: 2021-02-01
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Venumadhav Bhagavatula; Siu-Chuang Ivan Lu; Sang Won Son
- Web page: https://patentgrep.com/patent/US12113301B2

## CPC

- H01Q 5/42: using two or more imbricated arrays (H01Q5/49 takes precedence)
- H01Q 5/307: Individual or coupled radiating elements, each element being fed in an unspecified way
- H01Q 5/50: Feeding or matching arrangements for broad-band or multi-band operation
- H04B 1/005: {adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges}
- H04B 1/44: Transmit/receive switching
- H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72)
- H04B: TRANSMISSION

## Abstract

A radio frequency integrated circuit (RFIC) and method of communication are provided. The RFIC includes phased-locked loop (PLL) and data stream circuitry and a plurality of tiles in communication with the PLL and data stream circuitry. The plurality of tiles includes comprising at least one tile for each frequency band of the RFIC. The plurality of tiles are configured to communicate a data stream signal between tiles in a cascading sequence. Each tile of the plurality of tiles includes a plurality of up/down conversion mixers for converting the data stream signal between an intermediate frequency (IF) and a radio frequency (RF). Each tile also includes a plurality of front end (FE) elements, each in communication with a corresponding antenna and an up/down conversion mixer of the plurality of up/down conversion mixers.

## Claims

### Claim 1

A radio frequency integrated circuit (RFIC) comprising:
phase-locked loop (PLL) and data stream circuitry;
a plurality of tiles in communication with the PLL and data stream circuitry, wherein the plurality of tiles comprise at least one tile for each frequency band of the RFIC, wherein the plurality of tiles are configured to communicate a data stream signal through adjacent tiles of the plurality of tiles in a cascading sequence, and wherein each tile of the plurality of tiles comprises:
a plurality of up/down conversion mixers for converting the data stream signal between an intermediate frequency (IF) and a radio frequency (RF); and
a plurality of front end (FE) elements, each in communication with a corresponding antenna and an up/down conversion mixer of the plurality of up/down conversion mixers,
wherein the RFIC is a single-chip phased-array RFIC.

### Claim 2 (depends on 1)

The RFIC of claim 1, wherein:
the PLL and data stream circuitry provides a reference clock signal to each tile in the cascading sequence; and
each tile further comprises a plurality of clock multiplier circuits, and when a given tile of the plurality of tiles receives the reference clock signal:
the plurality of clock multiplier circuits multiply the reference clock signal by a predefined value to generate a respective clock frequency for the given tile; and
the given tile provides the reference clock signal to a next tile in the cascading sequence via a first through channel.

### Claim 3 (depends on 2)

The RFIC of claim 2, wherein tiles of different frequency bands are preset with different predefined values.

### Claim 4 (depends on 2)

The RFIC of claim 2, wherein each tile further comprises a demultiplexer, and when the given tile receives the data stream signal from the PLL and data stream circuitry in the cascading sequence:
the demultiplexer provides the data stream signal to the next tile in the cascading sequence via a second through channel when the given tile corresponds to an inactive channel, and provides the data stream signal to the plurality of up-down conversion mixers when the given tile corresponds to an active channel.

### Claim 5 (depends on 4)

The RFIC of claim 4, wherein each tile further comprises a two-way splitter/combiner, and when the given tile corresponds to the active channel:
the two-way splitter/combiner receives the data stream signal from the demultiplexer, and splits the data stream signal between the plurality of up/down conversion mixers; and
the plurality of up/down conversion mixers up-converts the data stream signals from the IF to the RF based on the clock frequency from the clock multiplier circuits.

### Claim 6 (depends on 5)

The RFIC of claim 5, wherein each of the plurality of FE elements comprises a phase shifter, a power amplifier, a low-noise amplifier, and a transmit/receive switch.

### Claim 7 (depends on 6)

The RFIC of claim 6, wherein:
the two-way splitter/combiner splits the data stream signal between two up/down conversion mixers, when the phase shifter is an RF phase shifter; and
the two-way splitter/converter splits the data stream signal between four up/down conversion mixers, when the phase shifter is a local oscillator (LO) phase shifter.

### Claim 8 (depends on 6)

The RFIC of claim 6, wherein each tile further comprises:
a two-way splitter/combiner that combines converted data stream signals from the plurality of up/down conversion mixers; and
a multiplexer that receives the combined converted data signal from the two-way splitter/combiner and outputs the combined converted data signal to the PLL and data stream circuitry, directly or via a previous tile in the cascading sequence.

### Claim 9 (depends on 5)

The RFIC of claim 5, wherein each tile further comprises a pair of two-way splitters/combiners that split the converted data stream signals to the plurality of FE elements for transmission of the converted data stream signals over the corresponding antennas.

### Claim 10 (depends on 2)

The RFIC of claim 2, wherein each tile further comprises a pair of two-way splitters/combiners, and when the given tile receives data stream signals from the corresponding antennas:
the plurality of FE elements provide the data stream signals to the pair of two-way splitters/combiners that combine the data stream signals; and
the pair of two-way splitters/combiners provide the combined data stream signals to the plurality of up/down conversion mixers that down-convert the combined data stream signals from the RF to the IF based on the clock frequency from the clock multiplier circuits.

### Claim 11 (depends on 10)

The RFIC of claim 10, wherein each of the plurality of FE elements comprises a phase shifter, a power amplifier, a low-noise amplifier, and a transmit/receive switch.

### Claim 12 (depends on 11)

The RFIC of claim 11, wherein:
the combined data stream signals are provided to two up/down conversion mixers, when the phase shifter is an RF phase shifter; and
the combined data stream signals are provided to four up/down conversion mixers, when the phase shifter is an LO phase shifter.

### Claim 13

A method for communicating a data stream signal via a radio frequency integrated circuit (RFIC), the method comprising:
receiving at least one data stream signal at one of a plurality of tiles of the RFIC, wherein the plurality of tiles comprises at least one tile for each frequency band of the RFIC, the plurality of tiles are configured to communicate through adjacent tiles of the plurality of tiles in a cascading sequence, and each tile of the plurality of tiles comprises a plurality of up/down conversion mixers and a plurality of front end (FE) elements, each of the plurality of FE elements being in communication with a corresponding antenna and an up/down conversion mixer of the plurality of up/down conversion mixers; and
converting the at least one data stream signal between an intermediate frequency (IF) and a radio frequency (RF) at the plurality of up/down conversion mixers of the one of the plurality of tiles,
wherein the RFIC is a single-chip phased-array RFIC.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
providing a reference clock signal from phase-locked loop (PLL) and data stream circuitry of the RFIC to each tile in the cascading sequence; and
when a given tile of the plurality of tiles receives the reference clock signal:
multiplying the reference clock signal by a predefined value at a plurality of clock multiplier circuits to generate a respective clock frequency for the given tile; and
providing the reference clock signal to a next tile in the cascading sequence via a first through channel.

### Claim 15 (depends on 14)

The method of claim 14, wherein tiles of different frequency bands are preset with different predefined values.

### Claim 16 (depends on 14)

The method of claim 14, wherein the at least one data stream signal is transmitted via the RFIC, and receiving the at least one data stream signal comprises:
providing a data stream signal from the PLL and data stream circuitry of the RFIC to one or more of a plurality of tiles of the RFIC in the cascading sequence.

### Claim 17 (depends on 16)

The method of claim 16, wherein converting the at least one data stream signal comprises:
when the given tile corresponds to an active channel:
up-converting the data stream signal from the IF to the RF at the plurality of up/down conversion mixers based on the clock frequency from the clock multiplier circuits; and
providing the up-converted data stream signal to the plurality of FE elements for transmission over the corresponding antennas; and
when the given tile corresponds to an inactive channel, providing the data stream signal to a next tile in the cascading sequence via a second through channel.

### Claim 18 (depends on 14)

The method of claim 14, wherein the at least one data stream signal is received via the RFIC, and receiving the at least one data stream signal comprises:
receiving data stream signals via antennas and corresponding FE elements of the one of the plurality of tiles of the RFIC.

### Claim 19 (depends on 18)

The method of claim 18, wherein converting the at least one data stream signal comprises:
down-converting the data stream signals from the RF to the IF at the plurality of up/down conversion mixers based on the clock frequency from the clock multiplier circuits.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
combining the down-converted data stream signals at a combiner to generate a combined data stream signal;
transmitting the combined data stream signal to the PLL and data stream circuitry, directly or via a previous tile in the cascading sequence.