# US 12,113,265 B2 · Dual-stripline with crosstalk cancellation

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- Number: US 12,113,265 B2
- Document ID: US12113265B2
- Status: Granted
- Kind: B2
- Application number: 17/214,111
- Filed: 2021-03-26
- Published: 2022-09-29
- Granted: 2024-10-08
- Earliest claimed: 2021-03-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Albert Sutono; Xiaoning Ye
- Web page: https://patentgrep.com/patent/US12113265B2

## CPC

- H01P 3/08: Microstrips; Strip lines
- H01P 3/085: {Triplate lines}
- H01P 3/088: {Stacked transmission lines}
- H05K 1/0228: {Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors (balanced signal pairs H05K1/0245)}
- H05K 1/0245: {Lay-out of balanced signal pairs, e.g. differential lines or twisted lines}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/65: Shapes or dispositions of interconnections
- H05K 1/0253: {Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings (H05K1/0251 takes precedence)}
- H10W 44/216: {Waveguides, e.g. strip lines}
- H10W 70/685: comprising multiple insulating layers
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H01P: WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE (operating at optical frequencies G02B)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Electronic structures including a dual-stripline with crosstalk cancellation are described. In an example, a printed circuit board (PCB), a package substrate or a semiconductor die includes a dual-stripline structure. The dual-stripline structure includes a first region including a first top line vertically over a first bottom line, and a second top line vertically over a second bottom line. The dual-stripline structure also includes a second region including the first top line vertically over the second bottom line, and the second top line vertically over the first bottom line. The dual-stripline structure also includes a transition region between the first region and the second region. The first bottom line and the second bottom line cross in the transition region.

## Claims

### Claim 1

A printed circuit board (PCB) comprising a dual-stripline structure, the dual-stripline structure comprising:
a first region comprising a first top line vertically over a first bottom line, and a second top line vertically over a second bottom line;
a second region comprising the first top line vertically over the second bottom line, and the second top line vertically over the first bottom line; and
a transition region between the first region and the second region, wherein the first bottom line and the second bottom line cross in the transition region.

### Claim 2 (depends on 1)

The PCB of claim 1, wherein the first bottom line crosses over the second bottom line in the transition region using a first via and a second via, the first via raising the first bottom line from a plane of the second bottom line to a plane of the first top line and the second top line, and the second via lowering the first bottom line from the plane of the first top line and the second top line to the plane of the second bottom line.

### Claim 3 (depends on 2)

The PCB of claim 2, further comprising:
a ground plane above and beneath the dual-stripline structure, wherein the ground plane does not include a void beneath the transition region.

### Claim 4 (depends on 2)

The PCB of claim 2, wherein the first top line and the second top line are spaced further apart from one another in the transition region than in the first region and in the second region.

### Claim 5 (depends on 1)

The PCB of claim 1, wherein the first bottom line crosses below the second bottom line in the transition region using a first via and a second via, the first via lowering the first bottom line from a plane of the second bottom line to a lower plane, and the second via raising the first bottom line from the lower plane to the plane of the second bottom line.

### Claim 6 (depends on 5)

The PCB of claim 5, further comprising:
a ground plane beneath the dual-stripline structure, wherein the ground plane includes a void beneath the transition region, and wherein the lower plane is in the void.

### Claim 7 (depends on 5)

The PCB of claim 5, wherein the first top line and the second top line are spaced a same distance from one another in the transition region as in the first region and in the second region.

### Claim 8

A package substrate, comprising:
a plurality of alternating organic dielectric layers and metal layers; and
a dual-stripline structure in the plurality of alternating organic dielectric layers and metal layers, the dual-stripline structure comprising:
a first region comprising a first top line vertically over a first bottom line, and a second top line vertically over a second bottom line;
a second region comprising the first top line vertically over the second bottom line, and the second top line vertically over the first bottom line; and
a transition region between the first region and the second region, wherein the first bottom line and the second bottom line cross in the transition region.

### Claim 9 (depends on 8)

The package substrate of claim 8, wherein the first bottom line crosses over the second bottom line in the transition region using a first via and a second via, the first via raising the first bottom line from a plane of the second bottom line to a plane of the first top line and the second top line, and the second via lowering the first bottom line from the plane of the first top line and the second top line to the plane of the second bottom line.

### Claim 10 (depends on 9)

The package substrate of claim 9, further comprising:
a ground plane beneath the dual-stripline structure, wherein the ground plane does not include a void beneath the transition region.

### Claim 11 (depends on 9)

The package substrate of claim 9, wherein the first top line and the second top line are spaced further apart from one another in the transition region than in the first region and in the second region.

### Claim 12 (depends on 8)

The package substrate of claim 8, wherein the first bottom line crosses below the second bottom line in the transition region using a first via and a second via, the first via lowering the first bottom line from a plane of the second bottom line to a lower plane, and the second via raising the first bottom line from the lower plane to the plane of the second bottom line.

### Claim 13 (depends on 12)

The package substrate of claim 12, further comprising:
a ground plane beneath the dual-stripline structure, wherein the ground plane includes a void beneath the transition region, and wherein the lower plane is in the void.

### Claim 14 (depends on 12)

The package substrate of claim 12, wherein the first top line and the second top line are spaced a same distance from one another in the transition region as in the first region and in the second region.

### Claim 15

A semiconductor die, comprising:
a semiconductor substrate;
a plurality of alternating dielectric layers and metal layers above the semiconductor substrate; and
a dual-stripline structure in the plurality of alternating dielectric layers and metal layers, the dual-stripline structure comprising:
a first region comprising a first top line vertically over a first bottom line, and a second top line vertically over a second bottom line;
a second region comprising the first top line vertically over the second bottom line, and the second top line vertically over the first bottom line; and
a transition region between the first region and the second region, wherein the first bottom line and the second bottom line cross in the transition region.

### Claim 16 (depends on 15)

The semiconductor die of claim 15, wherein the first bottom line crosses over the second bottom line in the transition region using a first via and a second via, the first via raising the first bottom line from a plane of the second bottom line to a plane of the first top line and the second top line, and the second via lowering the first bottom line from the plane of the first top line and the second top line to the plane of the second bottom line.

### Claim 17 (depends on 16)

The semiconductor die of claim 16, further comprising:
a ground plane beneath the dual-stripline structure, wherein the ground plane does not include a void beneath the transition region.

### Claim 18 (depends on 16)

The semiconductor die of claim 16, wherein the first top line and the second top line are spaced further apart from one another in the transition region than in the first region and in the second region.

### Claim 19 (depends on 15)

The semiconductor die of claim 15, wherein the first bottom line crosses below the second bottom line in the transition region using a first via and a second via, the first via lowering the first bottom line from a plane of the second bottom line to a lower plane, and the second via raising the first bottom line from the lower plane to the plane of the second bottom line.

### Claim 20 (depends on 19)

The semiconductor die of claim 19, further comprising:
a ground plane beneath the dual-stripline structure, wherein the ground plane includes a void beneath the transition region, and wherein the lower plane is in the void.

### Claim 21 (depends on 19)

The semiconductor die of claim 19, wherein the first top line and the second top line are spaced a same distance from one another in the transition region as in the first region and in the second region.