# US 12,113,134 B2 · Transistor, method of manufacturing transistor, and display device using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,134 B2 - Document ID: US12113134B2 - Status: Granted - Kind: B2 - Application number: 18/447,360 - Filed: 2023-08-10 - Published: 2023-11-30 - Granted: 2024-10-08 - Earliest claimed: 2018-09-26 - Assignees: Mikuni Electron Corporation - Applicants: Mikuni Electron Corporation - Inventors: Sakae Tanaka - Web page: https://patentgrep.com/patent/US12113134B2 ## CPC - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/6756: {Amorphous oxide semiconductors} - H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes} - H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/80: characterised by the materials - H10D 62/875: {being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874)} - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/60: wherein the TFTs are in active matrices - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering - H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)} - H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics} - H10K 59/1201: {Manufacture or treatment} - H10K 59/1213: {the pixel elements being TFTs} - H10K 59/124: Insulating layers formed between TFT elements and OLED elements - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract A transistor in an embodiment includes an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first region and a second region, a first gate electrode including a region overlapping the oxide semiconductor layer, the first gate electrode being arranged on a surface of the oxide semiconductor layer opposite to the substrate, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a first oxide conductive layer and a second oxide conductive layer between the oxide semiconductor layer and the substrate, the first oxide conductive layer and the second oxide conductive layer each including a region in contact with the oxide semiconductor layer. ## Claims ### Claim 1 A transistor comprising: an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first layer and a second layer; a first gate electrode including a region overlapping the oxide semiconductor layer; a first insulating layer between the first gate electrode and the oxide semiconductor layer; and a first oxide conductive layer and a second oxide conductive layer each including a region in contact with the oxide semiconductor layer; wherein the first layer of the oxide semiconductor layer and the second layer of the oxide semiconductor layer include a region overlapping each other, the first layer of the oxide semiconductor layer is arranged closer to the top surface of the substrate than the second layer of the oxide semiconductor layer, wherein an energy level at a lower end of the conduction band of the second layer of the oxide semiconductor layer is higher than an energy level at a lower end of the conduction band of the first layer of the oxide semiconductor layer. ### Claim 2 (depends on 1) The transistor according to claim 1, wherein the first gate electrode is arranged to face a surface of the oxide semiconductor layer opposite to a top surface of the substrate. ### Claim 3 (depends on 2) The transistor according to claim 2, further comprising a second insulating layer between the substrate and the oxide semiconductor layer; and a second gate electrode including a region overlapping the oxide semiconductor layer and the first gate electrode, the second gate electrode being arranged between the second insulating layer and the substrate. ### Claim 4 (depends on 3) The transistor according to claim 3, wherein a width of the first gate electrode in a channel length direction is larger than a width of the second gate electrode in the channel length direction. ### Claim 5 (depends on 1) The transistor according to claim 1, wherein the first oxide conductive layer and the second oxide conductive layer are arranged between the oxide semiconductor layer and the substrate. ### Claim 6 (depends on 1) The transistor according to claim 1, further comprising a second insulating layer between the substrate and the oxide semiconductor layer, the second insulating layer including a region in contact with the first layer of the oxide semiconductor layer. ### Claim 7 (depends on 1) The transistor according to claim 1, wherein an end part of the first oxide conductive layer and an end part of the second oxide conductive layer each overlap the first gate electrode. ### Claim 8 (depends on 1) The transistor according to claim 1, wherein a conductivity of the first layer of the oxide semiconductor layer is higher than a conductivity of the second layer of the oxide semiconductor layer. ### Claim 9 (depends on 1) The transistor according to claim 1, wherein a band gap of the first layer of the oxide semiconductor layer is smaller than a band gap of the second layer of the oxide semiconductor layer, and a work function of the first layer of the oxide semiconductor layer is larger than a work function of the second layer of the oxide semiconductor layer. ### Claim 10 (depends on 1) The transistor according to claim 1, wherein a band gap of the second layer of the oxide semiconductor layer is wider than a band gap of the first layer of the oxide semiconductor layer. ### Claim 11 (depends on 1) The transistor according to claim 1, wherein a carrier concentration of the second layer of the oxide semiconductor layer is lower than a carrier concentration of the first layer of the oxide semiconductor layer. ### Claim 12 (depends on 1) The transistor according to claim 1, wherein a carrier mobility of the first layer of the oxide semiconductor layer is higher than a carrier mobility of the second layer of the oxide semiconductor layer. ### Claim 13 (depends on 1) The transistor according to claim 1, wherein a crystallization ratio of the first layer of the oxide semiconductor layer is lower than a crystallization ratio of the second layer of the oxide semiconductor layer. ### Claim 14 (depends on 1) The transistor according to claim 1, wherein a film thickness of the first layer of the oxide semiconductor layer is larger than a film thickness of the second layer of the oxide semiconductor layer. ### Claim 15 (depends on 1) The transistor according to claim 1, wherein a material of the second layer of the oxide semiconductor layer is an oxide material containing amorphous Ga2O3. ### Claim 16 (depends on 15) The transistor according to claim 15, wherein a band gap of the second layer of the oxide semiconductor layer is larger than a band gap of the first layer of the oxide semiconductor layer by 1.0 eV or more. ### Claim 17 (depends on 1) The transistor according to claim 1, wherein the first oxide conductive layer and the second oxide conductive layer each have a region overlapping with the first gate electrode, the second oxide conductive layer has a pattern curved in a U shape in a planer view at least in a region overlapping with the first gate electrode, and the first oxide conductive layer has a linear pattern extending inward of the pattern curved in the U shape in the planer view. ### Claim 18 (depends on 1) The transistor according to claim 1, wherein the first oxide conductive layer and the second oxide conductive layer are arranged between the oxide semiconductor layer and the substrate. ### Claim 19 A transistor comprising: an oxide semiconductor layer on a substrate, the oxide semiconductor layer having a first surface on a side of the substrate and a second surface opposite to the first surface; a first gate electrode including a region overlapping the oxide semiconductor layer; a first insulating layer between the first gate electrode and the oxide semiconductor layer; and a first oxide conductive layer and a second oxide conductive layer each including a region in contact with the first surface of the oxide semiconductor layer; wherein an energy level at a lower end of the conduction band of the second surface of the oxide semiconductor layer is higher than an energy level at a lower end of the conduction band of the first surface of the oxide semiconductor layer. ### Claim 20 (depends on 19) The transistor according to claim 19, wherein the first gate electrode is arranged to face the second surface of the oxide semiconductor layer.