# US 12,113,133 B2 · Metal oxide transistor, display panel and display apparatus

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,113,133 B2
- Document ID: US12113133B2
- Status: Granted
- Kind: B2
- Application number: 17/564,045
- Filed: 2021-12-28
- Published: 2022-06-23
- Granted: 2024-10-08
- Earliest claimed: 2021-09-17
- Assignees: Wuhan Tianma Microelectronics Co., Ltd.
- Applicants: Wuhan Tianma Microelectronics Co., Ltd.
- Inventors: Qinyuan Zhang
- Web page: https://patentgrep.com/patent/US12113133B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10K 59/126: Shielding, e.g. light-blocking means over the TFTs
- H10K 59/1213: {the pixel elements being TFTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A metal oxide transistor, display panel and display apparatus are provided. The metal oxide transistor has characteristics of low off-state leakage current and high conductivity. In an embodiment, the metal oxide transistor includes first gate electrode, an active layer, second gate electrode, and source-drain electrode. Source-drain electrode includes source electrode and drain electrode. Active layer includes active sub-layers, active sub-layer includes metal oxide and has semiconductor zone. Active sub-layers includes first active sub-layer, second active sub-layer and third active sub-layer, first active sub-layer is located between second active sub-layer and first gate electrode, and third active sub-layer is located between second active sub-layer and second gate electrode. Semiconductor zone of first active sub-layer has an oxygen ion doping concentration CO_1, semiconductor zone of second active sub-layer has an oxygen ion doping concentration CO_2, and semiconductor zone of third active sub-layer has an oxygen ion doping concentration CO_3, where CO_1<CO_2, and CO_3<CO_2.

## Claims

### Claim 1

A metal oxide transistor, comprising a first gate electrode, an active layer, a second gate electrode, and a source-drain electrode that are stacked,
wherein the source-drain electrode comprises a source electrode and a drain electrode;
wherein the active layer comprises a plurality of active sub-layers, each of the plurality of active sub-layers comprises a metal oxide and defines a semiconductor zone;
wherein the plurality of active sub-layers comprises a first active sub-layer, a second active sub-layer, and a third active sub-layer, the first active sub-layer being located between the second active sub-layer and the first gate electrode, and the third active sub-layer being located between the second active sub-layer and the second gate electrode; and
wherein a semiconductor zone of the first active sub-layer has an oxygen ion doping concentration CO_1, a semiconductor zone of the second active sub-layer has an oxygen ion doping concentration CO_2, and a semiconductor zone of the third active sub-layer has an oxygen ion doping concentration CO_3, where CO_1<CO_2, and CO_3<CO_2.

### Claim 2 (depends on 1)

The metal oxide transistor according to claim 1, wherein the first active sub-layer, the second active sub-layer, and the third active sub-layer comprise a same metal oxide.

### Claim 3 (depends on 1)

The metal oxide transistor according to claim 1, wherein each of the first active sub-layer, the second active sub-layer, and the third active sub-layer comprises an indium-gallium-zinc oxide;
wherein the semiconductor zone of the first active sub-layer has an indium ion doping concentration CIn_1, the semiconductor zone of the second active sub-layer has an indium ion doping concentration CIn_2, and the semiconductor zone of the third active sub-layer has an indium ion doping concentration CIn_3, where CIn_1>CIn_2, and CIn_3>CIn_2; and/or
wherein the semiconductor zone of the first active sub-layer has a gallium ion doping concentration CGa_1, the semiconductor zone of the second active sub-layer has a gallium ion doping concentration CGa_2, and the semiconductor zone of the third active sub-layer has a gallium ion doping concentration CGa_3, where CGa_1<CGa_2, and CGa_3<CGa_2.

### Claim 4 (depends on 1)

The metal oxide transistor according to claim 1, wherein CO_1=CO_3.

### Claim 5 (depends on 1)

The metal oxide transistor according to claim 1, wherein the semiconductor zone of the active sub-layer comprises a first semiconductor zone, a second semiconductor zone, and a third semiconductor zone located between the first semiconductor zone and the second semiconductor zone; and
wherein the first semiconductor zone has an oxygen ion doping concentration lower than an oxygen ion doping concentration of the third semiconductor zone, or the third semiconductor zone has an oxygen ion doping concentration lower than an oxygen ion doping concentration of the second semiconductor zone.

### Claim 6 (depends on 1)

The metal oxide transistor according to claim 1, wherein a direction along which the first gate electrode, the active layer, the second gate electrode, and the source-drain electrode are stacked is defined as a first direction; and
wherein the first active sub-layer has a thickness d1 in the first direction, the second active sub-layer has a thickness d2 in the first direction, and the third active sub-layer has a thickness d3 in the first direction, where d2>d1, and d2>d3.

### Claim 7 (depends on 1)

The metal oxide transistor according to claim 1, wherein the metal oxide transistor further comprises a first insulating layer located between the first active sub-layer and the first gate electrode, and a second insulating layer located between the third active sub-layer and the second gate electrode;
wherein the plurality of active sub-layers further comprises a fourth active sub-layer located between the first active sub-layer and the first insulating layer, and/or a fifth active sub-layer located between the third active sub-layer and the second insulating layer;
wherein the fourth active sub-layer and the first active sub-layer comprise a same metal oxide, and a semiconductor zone of the fourth active sub-layer has an oxygen ion doping concentration CO_4, where CO_4>CO_1; and
wherein the fifth active sub-layer and the third active sub-layer comprise a same metal oxide, and a semiconductor zone of the fifth active sub-layer has an oxygen ion doping concentration CO_5, where CO_5>CO_3.

### Claim 8 (depends on 7)

The metal oxide transistor according to claim 7, wherein CO_4>CO_2 and CO_5>CO_2.

### Claim 9 (depends on 7)

The metal oxide transistor according to claim 7, wherein CO_4=CO_5.

### Claim 10 (depends on 7)

The metal oxide transistor according to claim 7, wherein each of the first active sub-layer, the third active sub-layer, the fourth active sub-layer, and the fifth active sub-layer comprises an indium-gallium-zinc oxide;
wherein the semiconductor zone of the first active sub-layer has an indium ion doping concentration CIn_1, the semiconductor zone of the fourth active sub-layer has an indium ion doping concentration CIn_4, the semiconductor zone of the third active sub-layer has an indium ion doping concentration CIn_3, and the semiconductor zone of the fifth active sub-layer has an indium ion doping concentration CIn_5, where CIn_4<CIn_1, and CIn_3<CIn_5; and/or
wherein the semiconductor zone of the first active sub-layer has a gallium ion doping concentration CGa_1, the semiconductor zone of the fourth active sub-layer has a gallium ion doping concentration CGa_4, the semiconductor zone of the third active sub-layer has a gallium ion doping concentration CGa_3, and the semiconductor zone of the fifth active sub-layer has a gallium ion doping concentration CGa_5, where CGa_4>CGa_1, and CGa_5>CGa_3.

### Claim 11 (depends on 7)

The metal oxide transistor according to claim 7, wherein a direction along which the first gate electrode, the active layer, the second gate electrode, and the source-drain electrode are stacked is defined as a first direction;
wherein the first active sub-layer has a thickness d1 in the first direction, and the fourth active sub-layer has a thickness d4 in the first direction, where d4<d1; and
wherein the third active sub-layer has a thickness d3 in the first direction, and the fifth active sub-layer has a thickness d5 in the first direction, where d5<d3.

### Claim 12 (depends on 7)

The metal oxide transistor according to claim 7, wherein a direction along which the first gate electrode, the active layer, the second gate electrode, and the source-drain electrode are stacked is defined as a first direction; and
wherein the fourth active sub-layer has a thickness d4 in the first direction, and the fifth active sub-layer has a thickness d5 in the first direction is d5, where d4≤5 nm, and d5≤5 nm.

### Claim 13 (depends on 1)

The metal oxide transistor according to claim 1, wherein the second gate electrode comprises a main gate electrode portion and an auxiliary gate electrode portion located at a side of the main gate electrode portion facing the active layer.

### Claim 14 (depends on 1)

The metal oxide transistor according to claim 1, wherein the active sub-layer further comprises a first conductive zone and a second conductive zone, the source electrode is electrically connected to the first conductive zone, and the drain electrode is electrically connected to the second conductive zone.

### Claim 15

A display panel, comprising:
a substrate; and
a plurality of pixel circuits located at a side of the substrate, wherein each of the plurality of pixel circuits comprises a metal oxide transistor comprising a first gate electrode, an active layer, a second gate electrode, and a source-drain electrode that are stacked,
wherein the source-drain electrode comprises a source electrode and a drain electrode;
wherein the active layer comprises a plurality of active sub-layers, and wherein each of the plurality of active sub-layers comprises a metal oxide and defines a semiconductor zone;
wherein the plurality of active sub-layers comprises a first active sub-layer, a second active sub-layer, and a third active sub-layer, the first active sub-layer being located between the second active sub-layer and the first gate electrode, and the third active sub-layer being located between the second active sub-layer and the second gate electrode; and
wherein a semiconductor zone of the first active sub-layer has an oxygen ion doping concentration CO_1, a semiconductor zone of the second active sub-layer has an oxygen ion doping concentration CO_2, and a semiconductor zone of the third active sub-layer has an oxygen ion doping concentration CO_3, where CO_1<CO_2, and CO_3<CO_2.

### Claim 16 (depends on 15)

The display panel according to claim 15, wherein each of the plurality of pixel circuits comprises a driving transistor and a type-I switching transistor, wherein a source electrode or a drain electrode of the type-I switching transistor is directly connected to a gate electrode of the driving transistor, and wherein the type-I switching transistor is the metal oxide transistor.

### Claim 17 (depends on 16)

The display panel according to claim 16, wherein each of the plurality of pixel circuits further comprises a type-II switching transistor, wherein a source electrode and a drain electrode of the type-II switching transistor are not directly connected to the gate electrode of the driving transistor; and
wherein the display panel further has a display zone comprising an optical component arrangement zone, one of the plurality of pixel circuits located in the optical component arrangement zone is a first pixel circuit, and in the first pixel circuit, the type-II switching transistor is the metal oxide transistor.

### Claim 18

A display apparatus comprising a display panel, wherein the display panel comprises a substrate and a plurality of pixel circuits located at a side of the substrate,
wherein each of the plurality of pixel circuits comprises a metal oxide transistor comprising a first gate electrode, an active layer, a second gate electrode, and a source-drain electrode that are stacked,
wherein the source-drain electrode comprises a source electrode and a drain electrode;
wherein the active layer comprises a plurality of active sub-layers, wherein each of the plurality of active sub-layers comprises a metal oxide and defines a semiconductor zone;
wherein the plurality of active sub-layers comprises a first active sub-layer, a second active sub-layer, and a third active sub-layer, the first active sub-layer being located between the second active sub-layer and the first gate electrode, and the third active sub-layer being located between the second active sub-layer and the second gate electrode; and
wherein a semiconductor zone of the first active sub-layer has an oxygen ion doping concentration CO_1, a semiconductor zone of the second active sub-layer has an oxygen ion doping concentration CO_2, and a semiconductor zone of the third active sub-layer has an oxygen ion doping concentration CO_3, where CO_1<CO_2, and CO_3<CO_2.