# US 12,113,131 B2 · Strain enhanced SiC power semiconductor device and method of manufacturing

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- Number: US 12,113,131 B2
- Document ID: US12113131B2
- Status: Granted
- Kind: B2
- Application number: 17/633,804
- Filed: 2020-08-07
- Published: 2022-09-22
- Granted: 2024-10-08
- Earliest claimed: 2019-08-09
- Assignees: Hitachi Energy Ltd
- Applicants: Hitachi Energy Ltd
- Inventors: Stephan Wirths; Lars Knoll
- Web page: https://patentgrep.com/patent/US12113131B2

## CPC

- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 12/032: {of vertical IGBTs}
- H10D 12/441: {Vertical IGBTs}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/796: {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 62/8325: {Silicon carbide}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.

## Claims

### Claim 1

A SiC transistor device comprising:
a SiC semiconductor substrate having a top surface and a bottom surface;
a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface;
a source structure formed in the top surface of the SiC epitaxial layer, the source structure having a top surface;
a source contact structure electrically coupled to the top surface of the source structure;
a gate structure including a gate dielectric, a metal gate, and a gate insulation;
a first backside metal contact on the bottom surface of the SiC semiconductor substrate;
a stress inducing layer on the first backside metal contact; and
a second backside metal contact on the stress inducing layer.

### Claim 2 (depends on 1)

The SiC transistor device according to claim 1, wherein the second backside metal contact comprises at least one of titanium, nickel, aluminum or silver.

### Claim 3 (depends on 1)

The SiC transistor device according to claim 1, further comprising a second stress inducing layer on the gate structure.

### Claim 4 (depends on 1)

The SiC transistor device according to claim 1, further comprising a structured and electrically insulating second stress inducing layer on the top surface of the SiC epitaxial layer.

### Claim 5 (depends on 1)

The SiC transistor device according to claim 1, further comprising a second stress inducing layer on the gate structure.

### Claim 6 (depends on 1)

The SiC transistor device according to claim 1, wherein the stress inducing layer induces a tensile or compressive stress in a range of 500 MPa to 2000 MPa.

### Claim 7 (depends on 1)

The SiC transistor device according to claim 1, further comprising a structured and electrically insulating stress inducing layer on the top surface of the SiC epitaxial layer, wherein the source contact structure is electrically coupled to the top surface of the source structure through the structured and electrically insulating stress inducing layer.

### Claim 8 (depends on 7)

The SiC transistor device according to claim 7, wherein the structured and electrically insulating stress inducing layer induces a tensile or compressive stress in a range of 500 MPa to 2000 MPa.

### Claim 9 (depends on 1)

The SiC transistor device according to claim 1, further comprising a first contact layer electrically contacting the source contact structure and a second contact layer electrically contacting the metal gate, wherein the first contact layer or the second contact layer is at least partially covered with a passivation layer.

### Claim 10 (depends on 1)

The SiC transistor device according to claim 1, wherein the SiC semiconductor substrate and the SiC epitaxial layer are both a 4H-SiC of n-type.

### Claim 11 (depends on 1)

The SiC transistor device according to claim 1, wherein the stress inducing layer has a thickness between about 1 nm and 1000 nm.

### Claim 12 (depends on 1)

The SiC transistor device according to claim 1, wherein the stress inducing layer comprises silicon nitride.

### Claim 13 (depends on 1)

The SiC transistor device according to claim 1, wherein the stress inducing layer comprises titanium nitride.

### Claim 14 (depends on 1)

The SiC transistor device according to claim 1, wherein the SiC transistor device is a metal-oxide-semiconductor field-effect transistor (MOSFET).

### Claim 15 (depends on 1)

The SiC transistor device according to claim 1, wherein the SiC transistor device is an insulated-gate bipolar transistor (IGBT).

### Claim 16

A method of manufacturing a SiC transistor device comprising:
forming a SiC semiconductor substrate having a top surface and a bottom surface;
forming epitaxially a SiC epitaxial layer on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface;
forming a source structure in the top surface of the SiC epitaxial layer, the source structure having a top surface;
forming a source contact structure electrically coupled to the top surface of the source structure;
forming a gate structure on the top surface of the SiC epitaxial layer, wherein the gate structure includes a gate dielectric and a metal gate;
forming a first backside metal contact on the bottom surface of the SiC semiconductor substrate;
forming a stress inducing layer on the first backside metal contact;
structuring the stress inducing layer; and
forming a second backside metal contact on the structured stress inducing layer.

### Claim 17 (depends on 16)

The method according to claim 16, further comprising forming a stress inducing layer at the gate structure.

### Claim 18 (depends on 16)

The method according to claim 16, further comprising forming an electrically insulating stress inducing layer on the top surface of the SiC epitaxial layer and structuring the electrically insulating stress inducing layer, wherein the source contact structure is electrically coupled to the top surface of the source structure through the structured electrically insulating stress inducing layer and the gate structure is formed on the electrically insulating stress inducing layer.

### Claim 19 (depends on 16)

The method according to claim 16, further comprising forming a first contact layer electrically contacting the source contact structure and forming a second contact layer electrically contacting the metal gate.

### Claim 20

A method of manufacturing a SiC transistor device comprising:
forming a SiC semiconductor substrate having a top surface and a bottom surface;
forming epitaxially a SiC epitaxial layer on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface;
forming a source structure in the top surface of the SiC epitaxial layer, the source structure having a top surface;
forming an electrically insulating first stress inducing layer on the top surface of the SiC epitaxial layer;
structuring the electrically insulating first stress inducing layer;
forming a source contact structure electrically coupled to the top surface of the source structure;
forming a gate structure on the top surface of the SiC epitaxial layer, wherein the gate structure includes a metal gate;
forming a first backside metal contact on the bottom surface of the SiC semiconductor substrate;
forming a second stress inducing layer on the first backside metal contact;
structuring the second stress inducing layer; and
forming a second backside metal contact on the structured second stress inducing layer.