# US 12,113,130 B2 · Transistor and methods of forming integrated circuitry

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,113,130 B2
- Document ID: US12113130B2
- Status: Granted
- Kind: B2
- Application number: 18/195,480
- Filed: 2023-05-10
- Published: 2023-09-28
- Granted: 2024-10-08
- Earliest claimed: 2019-08-09
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hung-Wei Liu; Sameer Chhajed; Jeffery B. Hull; Anish A Khandekar
- Web page: https://patentgrep.com/patent/US12113130B2

## CPC

- H10D 30/711: {having floating bodies}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 62/40: Crystalline structures
- H10D 86/0229: {characterised by control of the annealing or irradiation parameters}
- H10P 14/3256: {Microstructure}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 14/3816: {Pulsed laser beam}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.

## Claims

### Claim 1

A transistor comprising:
a top source/drain region having a first conductivity-increasing dopant therein at a concentration rendering semiconductor material of the top source/drain region to be conductive;
a bottom source/drain region having a second conductivity-increasing dopant therein at a concentration rendering semiconductor material of the bottom source/drain region to be conductive;
a channel region vertically between the top and bottom source/drain regions;
a gate operatively laterally adjacent the channel region;
an upper portion of the channel region adjacent the top source/drain region having a non-conductive concentration of the first conductivity-increasing dopant therein; and
a lower portion of the channel region adjacent the bottom source/drain region having a non-conductive concentration of the second conductivity increasing dopant therein, the upper portion being vertically thicker than the lower portion.

### Claim 2 (depends on 1)

The transistor of claim 1 wherein the first conductivity-increasing dopant and the second conductivity-increasing dopant are the same.

### Claim 3 (depends on 1)

The transistor of claim 1 wherein the first conductivity-increasing dopant and the second conductivity-increasing dopant are different.

### Claim 4 (depends on 1)

The transistor of claim 1 wherein the upper portion is no more than 33% of vertical thickness of the channel region.

### Claim 5 (depends on 4)

The transistor of claim 4 wherein the upper portion is no more than 25% of the vertical thickness of the channel region.

### Claim 6 (depends on 1)

The transistor of claim 1 wherein the upper portion is at least 2.0 times vertically thicker than the lower portion.

### Claim 7 (depends on 6)

The transistor of claim 6 wherein the upper portion is at least 2.5 times vertically thicker than the lower portion.

### Claim 8 (depends on 1)

The transistor of claim 1 wherein concentration of the first conductivity-increasing dopant in the upper portion of the channel region is not constant.

### Claim 9 (depends on 8)

The transistor of claim 8 wherein concentration of the first conductivity-increasing dopant in the upper portion of the channel region decreases moving vertically deeper into said upper portion.

### Claim 10 (depends on 9)

The transistor of claim 9 wherein the upper portion is no more than 33% of vertical thickness of the channel region.

### Claim 11 (depends on 1)

The transistor of claim 1 wherein concentration of the second conductivity-increasing dopant in the lower portion of the channel region is not constant.

### Claim 12 (depends on 8)

The transistor of claim 8 wherein concentration of the second conductivity-increasing dopant in the lower portion of the channel region increases moving vertically deeper into said lower portion.

### Claim 13 (depends on 1)

The transistor of claim 1 wherein,
concentration of the first conductivity-increasing dopant in the upper portion of the channel region is not constant and decreases moving vertically deeper into said upper portion; and
concentration of the second conductivity-increasing dopant in the lower portion of the channel region is not constant and increases moving vertically deeper into said lower portion.

### Claim 14

A transistor comprising:
a top source/drain region having a first conductivity-increasing dopant therein at a concentration rendering semiconductor material of the top source/drain region to be conductive;
a bottom source/drain region having a second conductivity-increasing dopant therein at a concentration rendering semiconductor material of the bottom source/drain region to be conductive;
a channel region vertically between the top and bottom source/drain regions;
a gate operatively laterally adjacent the channel region;
an upper portion of the channel region adjacent the top source/drain region having a non-conductive concentration of the first conductivity-increasing dopant therein;
a lower portion of the channel region adjacent the bottom source/drain region having a non-conductive concentration of the second conductivity increasing dopant therein, the upper portion being vertically thicker than the lower portion; and
an intervening region of the channel region vertically between the upper and lower portions of the channel regions, the intervening region being thicker than the upper portion of the channel region.

### Claim 15 (depends on 14)

The transistor of claim 14 wherein the non-conductive concentration of the second conductivity increasing dopant in the lower portion of the channel region is less than 1×1018 dopant atoms/cm3.

### Claim 16 (depends on 14)

The transistor of claim 14 wherein the non-conductive concentration of the second conductivity increasing dopant in the upper portion of the channel region is less than 1×1018 dopant atoms/cm3.

### Claim 17 (depends on 14)

The transistor of claim 14 wherein the top source/drain region and the channel region have an interface that is flat and horizontal.

### Claim 18 (depends on 14)

The transistor of claim 14 wherein the bottom source/drain region and the channel region have an interface that is flat and horizontal.

### Claim 19

A transistor comprising:
a top source/drain region having a first conductivity-increasing dopant therein at a concentration rendering semiconductor material of the top source/drain region to be conductive;
a bottom source/drain region having a second conductivity-increasing dopant therein at a concentration rendering semiconductor material of the bottom source/drain region to be conductive;
a channel region vertically between the top and bottom source/drain regions;
a gate operatively laterally adjacent the channel region;
an upper portion of the channel region adjacent the top source/drain region having a non-conductive concentration of the first conductivity-increasing dopant therein;
a lower portion of the channel region adjacent the bottom source/drain region having a non-conductive concentration of the second conductivity increasing dopant therein, the upper portion being vertically thicker than the lower portion; and
an intervening region of the channel region vertically between the upper and lower portions of the channel regions, the intervening region being thicker than the lower portion of the channel region.

### Claim 20 (depends on 19)

The transistor of claim 19 wherein the intervening region is thicker than the upper portion of the channel region.