# US 12,113,129 B2 · Semiconductor device, array structure of semiconductor devices, neuromorphic circuit including the semiconductor devices, and computing apparatus including the neuromorphic circuit

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- Number: US 12,113,129 B2
- Document ID: US12113129B2
- Status: Granted
- Kind: B2
- Application number: 17/716,460
- Filed: 2022-04-08
- Published: 2023-02-09
- Granted: 2024-10-08
- Earliest claimed: 2021-08-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jaechul Park; Youngkwan Cha
- Web page: https://patentgrep.com/patent/US12113129B2

## CPC

- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10B 51/30: characterised by the memory core region
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/689: {having ferroelectric layers}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 51/10: characterised by the top-view layout
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a semiconductor layer extending in a first direction and including a source region and a drain region, which are apart from each other in the first direction; an insulating layer surrounding the semiconductor layer; a first gate electrode layer surrounding the insulating layer; a ferroelectric layer provided on the first gate electrode layer; and a second gate electrode layer provided on the ferroelectric layer.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor layer extending in a first direction and comprising a source region and a drain region, which are apart from each other in the first direction;
an insulating layer surrounding the semiconductor layer;
a first gate electrode layer surrounding the insulating layer;
a ferroelectric layer on the first gate electrode layer; and
a second gate electrode layer on the ferroelectric layer,
wherein between the source region and the drain region, a ratio C2/C1 of a second capacitance C2 between the first gate electrode layer and the second gate electrode layer to a first capacitance C1 between the semiconductor layer and the first gate electrode layer is about 1/20 to about ⅕.

### Claim 2 (depends on 1)

The semiconductor device of claim 1,
wherein the insulating layer and the first gate electrode layer have an all-around shape surrounding the semiconductor layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1,
wherein a first ratio r1=ε1/t1 of a first dielectric constant ε1 of the insulating layer to a first thickness t1 of the insulating layer is equal to a second ratio r2=ε2/t2 of a second dielectric constant ε2 of the ferroelectric layer to a second thickness t2 of the ferroelectric layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3,
wherein a ratio A2/A1 of a second area A2 of a surface of the ferroelectric layer, which contacts the first gate electrode layer between the source region and the drain region, to a first area A1 of a surface of the insulating layer, which contacts the first gate electrode layer between the source region and the drain region, is about 1/20 to about ⅕.

### Claim 5 (depends on 1)

The semiconductor device of claim 1,
wherein a length of the ferroelectric layer in the first direction is about 10 nm to about 20 nm.

### Claim 6 (depends on 1)

The semiconductor device of claim 1,
wherein a first length of the insulating layer in the first direction between the source region and the drain region is greater than a second length of the ferroelectric layer in the first direction between the source region and the drain region.

### Claim 7 (depends on 1)

The semiconductor device of claim 1,
wherein a second width of the ferroelectric layer in a second direction crossing the first direction is equal to a third width of the first gate electrode layer in the second direction.

### Claim 8 (depends on 1)

The semiconductor device of claim 1,
wherein a second width of the ferroelectric layer in a second direction crossing the first direction is greater than a third width of the first gate electrode layer in the second direction.

### Claim 9 (depends on 1)

The semiconductor device of claim 1,
wherein a second length of the ferroelectric layer in the first direction is equal to a third length of the second gate electrode layer in the first direction.

### Claim 10 (depends on 1)

The semiconductor device of claim 1,
wherein a second width of the ferroelectric layer in a second direction crossing the first direction is equal to a fourth width of the second gate electrode layer in the second direction.

### Claim 11 (depends on 1)

The semiconductor device of claim 1,
wherein the semiconductor layer comprises:
a front surface and a rear surface, which are opposite each other in a second direction crossing the first direction; and
an upper surface and a lower surface, which are opposite each other in a third direction perpendicular to both the first direction and the second direction,
wherein the insulating layer surrounds the semiconductor layer and contacts the front surface, the rear surface, the upper surface, and the lower surface of the semiconductor layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11,
wherein the first direction and the second direction are perpendicular to each other.

### Claim 13 (depends on 11)

The semiconductor device of claim 11,
wherein the ferroelectric layer and the second gate electrode layer cover the first gate electrode layer on a side of the upper surface of the semiconductor layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13,
wherein the ferroelectric layer and the second gate electrode layer extend to cover the first gate electrode layer on a side of the front surface and a side of the rear surface of the semiconductor layer.

### Claim 15

A semiconductor device array structure comprising:
a plurality of gate lines side by side in a first direction and each extending in a second direction;
a plurality of semiconductor structures side by side in the second direction and crossing the plurality of gate lines, each of the plurality of semiconductor structures extending in the first direction; and
a plurality of ferroelectric structures between the plurality of gate lines and the plurality of semiconductor structures,
wherein each of the plurality of semiconductor structures comprises a semiconductor layer extending in the first direction and comprising a plurality of source regions and a plurality of drain regions which are apart from each other in the first direction, an insulating layer surrounding the semiconductor layer, and a first gate electrode layer surrounding the insulating layer,
between a first drain region and a first source region which are adjacent to each other among the plurality of source regions and the plurality of drain regions, a ratio C2/C1 of a second capacitance C2 between the first gate electrode layer and one of the plurality of gate lines, which is adjacent to the first gate electrode layer, to a first capacitance C1 between the semiconductor layer and the first gate electrode layer is about 1/20 to about ⅕.

### Claim 16 (depends on 15)

The semiconductor device of claim 15,
wherein the plurality of ferroelectric structures are side by side in the first direction, and each of the plurality of ferroelectric structures extends in the second direction.

### Claim 17 (depends on 15)

The semiconductor device of claim 15,
wherein the plurality of ferroelectric structures are apart from each other and at a plurality of crossing points between the plurality of gate lines and the plurality of semiconductor structures.

### Claim 18

A neuromorphic circuit comprising:
a pre-synaptic neuron circuit;
a pre-synaptic line extending in a first direction from the pre-synaptic neuron circuit;
a post-synaptic neuron circuit;
a post-synaptic line extending from the post-synaptic neuron circuit in a second direction crossing the first direction; and
a synaptic circuit at an intersection between the pre-synaptic line and the post-synaptic line,
wherein the synaptic circuit comprises a semiconductor device comprising a semiconductor layer extending in the first direction and comprising a source region and a drain region, which are apart from each other in the first direction, an insulating layer surrounding the semiconductor layer, a first gate electrode layer surrounding the insulating layer, a ferroelectric layer on the first gate electrode layer, and a second gate electrode layer provided on the ferroelectric layer,
wherein between the source region and the drain region, a ratio C2/C1 of a second capacitance C2 between the first gate electrode layer and the second gate electrode layer to a first capacitance C1 between the semiconductor layer and the first gate electrode layer is about 1/20 to about ⅕.

### Claim 19 (depends on 18)

The neuromorphic circuit of claim 18,
wherein a first ratio r1=ε1/t1 of a first dielectric constant ε1 of the insulating layer to a first thickness t1 of the insulating layer is equal to a second ratio r2=ε2/t2 of a second dielectric constant &2 of the ferroelectric layer to a second thickness t2 of the ferroelectric layer, and
a ratio A2/A1 of a second area A2 of a surface of the ferroelectric layer, which contacts the first gate electrode layer between the source region and the drain region, to a first area A1 of a surface of the insulating layer, which contacts the first gate electrode layer between the source region and the drain region, is about 1/20 to about ⅕.

### Claim 20 (depends on 18)

A neuromorphic computing apparatus comprising:
an input device;
the neuromorphic circuit of claim 18, the neuromorphic circuit being configured to store and output specific information based on a signal from the input device; and
a processor configured to process the information output from the neuromorphic circuit.