# US 12,113,128 B2 · DMOS transistor having thick gate oxide and STI and method of fabricating > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,128 B2 - Document ID: US12113128B2 - Status: Granted - Kind: B2 - Application number: 17/330,095 - Filed: 2021-05-25 - Published: 2021-09-09 - Granted: 2024-10-08 - Earliest claimed: 2018-11-02 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Alexei Sadovnikov; Natalia Lavrovskaya - Web page: https://patentgrep.com/patent/US12113128B2 ## CPC - H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]} - H10D 30/65: Lateral DMOS [LDMOS] FETs - H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]} - H10D 30/0281: {of lateral DMOS [LDMOS] FETs} - H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)} - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor} - H10D 64/111: {Field plates} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation} - H10D 64/01346: {in a gaseous ambient using an oxygen or a water vapour, e.g. oxidation through a layer (H10D64/01344 takes precedence)} - H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An integrated circuit chip and a method of fabricating the IC chip to include a transistor having a thick gate oxide in combination with STI. The method provides a wafer for which a source region location, a drain contact region location, an extended drain region location and a gate region location have been defined and forms an STI structure overlying the extended drain region location. After growing a gate oxide layer over the gate region location and a portion of the extended drain region location, the method forms a gate structure on the gate oxide layer, the gate structure having a gap overlying the intersection of an edge of the STI structure with the gate oxide layer. ## Claims ### Claim 1 An integrated circuit (IC) chip having a double-diffused metal oxide silicon (DMOS) transistor, the transistor comprising: a source region having a first dopant type; an extended drain region coupled to a drain contact region, the extended drain region and the drain contact region having the first dopant type; a gate region having a second dopant type that is opposite the first dopant type; a shallow trench isolation (STI) structure overlying the extended drain region; a gate oxide layer overlying the gate region and a portion of the extended drain region; a gate structure on the gate oxide layer, the gate structure having a gap overlying an intersection of an edge of the STI structure with the gate oxide layer, the gap filled with a dielectric; and a sidewall spacer on a sidewall surface of the gate structure within the gap between the dielectric and the sidewall surface. ### Claim 2 (depends on 1) The IC chip as recited in claim 1 wherein the gate oxide layer has a thickness that is at least five percent of the thickness of the STI structure. ### Claim 3 An integrated circuit (IC) chip having a double-diffused metal oxide silicon (DMOS) transistor, the transistor comprising: a source region having a first dopant type; an extended drain region coupled to a drain contact region, the extended drain region and the drain contact region having the first dopant type; a gate region having a second dopant type that is opposite the first dopant type; a shallow trench isolation (STI) structure overlying the extended drain region; a gate oxide layer overlying the gate region and a portion of the extended drain region; and a gate structure on the gate oxide layer, the gate structure having a gap, having a width of between 0.4 and 1.0 microns, overlying an intersection of an edge of the STI structure with the gate oxide layer, the gap filled with a dielectric. ### Claim 4 (depends on 3) The IC chip as recited in claim 3 wherein the gate structure comprises a polysilicon layer. ### Claim 5 (depends on 4) The IC chip as recited in claim 4 wherein the gate structure further comprises dielectric sidewall spacers. ### Claim 6 (depends on 5) The IC chip as recited in claim 5 wherein the gate structure further comprises a silicide layer on the polysilicon layer. ### Claim 7 (depends on 6) The IC chip as recited in claim 6 further comprising an inter-level dielectric (ILD) material overlying the source region, the extended drain region, the drain contact region, the gate region, the STI structure, the gate oxide layer and the gate structure, the ILD material filling the gap. ### Claim 8 An integrated circuit (IC), comprising: a source region having a first conductivity type located over a semiconductor layer having a second opposite conductivity type; a drain region and a drain contact region within the drain region, the drain region and the drain contact region located over the semiconductor layer and having the first conductivity type; a gate structure having a nonlinear bottom surface overlying the semiconductor layer and having a dielectric filled gap over the drain region; and a shallow trench isolation (STI) structure overlying the drain region and having an interface with the drain region that intersects a top surface of the semiconductor layer under the gap. ### Claim 9 (depends on 8) The IC as recited in claim 8, further comprising a gate oxide layer between the top surface and the gate structure, the gate oxide layer having a thickness that is at least five percent of a thickness of the STI structure. ### Claim 10 An integrated circuit (IC), comprising: a source region having a first conductivity type located over a semiconductor layer having a second opposite conductivity type; a drain region and a drain contact region within the drain region, the drain region and the drain contact region located over the semiconductor layer and having the first conductivity type; a gate structure overlying the semiconductor layer and having a dielectric filled gap, having a width of between 0.4 and 1.0 microns, over the drain region; and a shallow trench isolation (STI) structure overlying the drain region and having an interface with the drain region that intersects a top surface of the semiconductor layer under the gap. ### Claim 11 (depends on 8) The IC as recited in claim 8 wherein the gate structure comprises polysilicon. ### Claim 12 (depends on 11) The IC as recited in claim 11 wherein the gate structure further comprises a silicide layer on the polysilicon layer. ### Claim 13 (depends on 8) The IC as recited in claim 8 wherein the gate structure further comprises dielectric sidewall spacers. ### Claim 14 (depends on 8) The IC as recited in claim 8, further comprising an inter-level dielectric material overlying the semiconductor layer and, the inter-level dielectric material filling the gap. ### Claim 15 A transistor, comprising: a source region and a drain region both having a first conductivity type and located over a semiconductor layer having a second opposite conductivity type; a gate structure having a nonlinear bottom surface that overlies the drain region and extends to the source region, the gate structure having a dielectric filled gap over the drain region; and a shallow trench isolation (STI) structure overlying the drain region and having an interface with the drain region that intersects a top surface of the semiconductor layer under the gap. ### Claim 16 (depends on 15) The transistor as recited in claim 15, further comprising an inter-level dielectric material overlying the substrate, the inter-level dielectric material filling the gap. ### Claim 17 (depends on 15) The transistor as recited in claim 15, wherein the transistor is a double-diffused metal oxide silicon (DMOS) transistor, and the drain region is an extended drain region that extends from a drain contact toward the source region. ### Claim 18 (depends on 15) The transistor as recited in claim 15, wherein the first conductivity type is n-type and the second conductivity type is p-type. ### Claim 19 (depends on 8) The IC as recited in claim 8, wherein the semiconductor layer is a substrate. ### Claim 20 (depends on 8) The IC as recited in claim 8, wherein a silicide layer is formed on the gate structure but not on the source region. ### Claim 21 (depends on 8) The IC as recited in claim 8, wherein a silicide layer is formed on the gate structure but not on the drain region. ### Claim 22 (depends on 15) The transistor as recited in claim 15, wherein the semiconductor layer is a substrate. ### Claim 23 (depends on 15) The transistor as recited in claim 15, wherein a silicide layer is formed on the gate structure but not on the source region. ### Claim 24 (depends on 15) The transistor as recited in claim 15, wherein a silicide layer is formed on the gate structure but not on the drain region. ### Claim 25 An integrated circuit (IC) chip having a double-diffused metal oxide silicon (DMOS) transistor, the transistor comprising: a source region having a first dopant type; an extended drain region coupled to a drain contact region, the extended drain region and the drain contact region having the first dopant type; a gate region having a second dopant type that is opposite the first dopant type; a shallow trench isolation (STI) structure overlying the extended drain region; a gate oxide layer overlying the gate region and a portion of the extended drain region; and a gate structure entirely on the gate oxide layer, the gate structure having a gap overlying an intersection of an edge of the STI structure with the gate oxide layer, the gap filled with a dielectric. ### Claim 26 An integrated circuit (IC) chip having a double-diffused metal oxide silicon (DMOS) transistor, the transistor comprising: a source region having a first dopant type; an extended drain region coupled to a drain contact region, the extended drain region and the drain contact region having the first dopant type; a gate region having a second dopant type that is opposite the first dopant type; a shallow trench isolation (STI) structure overlying the extended drain region; a gate oxide layer overlying the gate region and a portion of the extended drain region; and a gate structure on the gate oxide layer, the gate structure having a gap overlying an intersection of an edge of the STI structure with the gate oxide layer, the gap filled with a dielectric, a surface of the gate oxide layer being nonlinear beneath the gap. ### Claim 27 An integrated circuit (IC) chip having a double-diffused metal oxide silicon (DMOS) transistor, the transistor comprising: a source region having a first dopant type; an extended drain region coupled to a drain contact region, the extended drain region and the drain contact region having the first dopant type; a gate region having a second dopant type that is opposite the first dopant type; a shallow trench isolation (STI) structure overlying the extended drain region; a gate oxide layer overlying the gate region, a portion of the extended drain region and no portion of the source region; and a gate structure on the gate oxide layer, the gate structure having a gap overlying an intersection of an edge of the STI structure with the gate oxide layer, the gap filled with a dielectric. ### Claim 28 An integrated circuit (IC), comprising: a source region having a first conductivity type located over a semiconductor layer having a second opposite conductivity type; a drain region and a drain contact region within the drain region, the drain region and the drain contact region located over the semiconductor layer and having the first conductivity type; a gate structure overlying the semiconductor layer and having a dielectric filled gap over the drain region; and a nonlinear shallow trench isolation (STI) structure overlying the drain region and having an interface with the drain region that intersects a top surface of the semiconductor layer under the gap. ### Claim 29 A transistor, comprising: a source region and a drain region both having a first conductivity type and located over a semiconductor layer having a second opposite conductivity type; a gate structure that overlies the drain region and extends to the source region, the gate structure having a dielectric filled gap over the drain region; and a nonlinear shallow trench isolation (STI) structure overlying the drain region and having an interface with the drain region that intersects a top surface of the semiconductor layer under the gap.