# US 12,113,122 B2 · Dummy fin profile control to enlarge gate process window

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- Number: US 12,113,122 B2
- Document ID: US12113122B2
- Status: Granted
- Kind: B2
- Application number: 18/178,140
- Filed: 2023-03-03
- Published: 2023-06-29
- Granted: 2024-10-08
- Earliest claimed: 2020-05-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shih-Yao Lin; Pei-Hsiu Wu; Chih Ping Wang; Chih-Han Lin; Jr-Jung Lin; Yun Ting Chou; Chen-Yu Wu
- Web page: https://patentgrep.com/patent/US12113122B2

## CPC

- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

## Claims

### Claim 1

A device comprising:
a semiconductor substrate;
isolation regions over a bulk portion of the semiconductor substrate;
a semiconductor fin protruding higher than top surfaces of the isolation regions;
a dielectric dummy fin protruding higher than the top surfaces of the isolation regions, wherein the dielectric dummy fin comprises a first sidewall; and
a dielectric dummy strip underlying and joined to the dielectric dummy fin, wherein the dielectric dummy strip is in the isolation regions, and wherein the dielectric dummy strip comprises a second sidewall contacting one of the isolation regions to form an interface, and wherein the first sidewall of the dielectric dummy fin is more tilted than the interface.

### Claim 2 (depends on 1)

The device of claim 1, wherein the dielectric dummy fin has a first width at a first top surface level of the isolation regions, and a second width at a second top surface level of the dielectric dummy fin, and wherein from the first top surface level to the second top surface level, the first sidewall is straight, and wherein the second width is smaller than the first width.

### Claim 3 (depends on 2)

The device of claim 2, wherein the dielectric dummy strip has a third width at a bottom surface level of the isolation regions, and the third width is smaller than the first width.

### Claim 4 (depends on 3)

The device of claim 3, wherein from the first top surface level to the bottom surface level, the second sidewall is straight.

### Claim 5 (depends on 1)

The device of claim 1, wherein the dielectric dummy fin has a first height smaller than a second height of the semiconductor fin.

### Claim 6 (depends on 1)

The device of claim 1, wherein the dielectric dummy fin has a first height equal to a second height of the semiconductor fin.

### Claim 7 (depends on 1)

The device of claim 1 further comprising:
a gate stack on the semiconductor fin; and
a gate isolation region over and contacting both of the dielectric dummy fin and the gate stack.

### Claim 8 (depends on 7)

The device of claim 7, wherein the gate stack comprises a gate dielectric and a gate electrode on the gate dielectric, wherein the gate isolation region is in physical contact with the gate electrode.

### Claim 9 (depends on 7)

The device of claim 7, wherein the gate isolation region comprises:
a first slanted-and-straight bottom surface; and
a second slanted-and-straight bottom surface joined to the first slanted-and-straight bottom surface to form a V-shaped bottom.

### Claim 10 (depends on 1)

The device of claim 1, wherein the dielectric dummy fin comprises a plurality of sub-layers.

### Claim 11

A device comprising:
a shallow trench isolation region;
a dielectric dummy strip contacting the shallow trench isolation region to form a first interface, wherein a bottom surface of the shallow trench isolation region forms a first angle with the first interface;
a dielectric dummy fin over and joined to the dielectric dummy strip;
a first protruding semiconductor fin and a second protruding semiconductor fin on opposing sides of the dielectric dummy fin;
a first gate stack on the first protruding semiconductor fin, wherein the first gate stack contacts the dielectric dummy fin to form a second interface, and wherein a top surface of the shallow trench isolation region forms a second angle with the second interface, and wherein the second angle is greater than the first angle;
a second gate stack on the second protruding semiconductor fin; and
a gate isolation region between, and contacting, the first gate stack and the second gate stack, wherein the gate isolation region is over and contacting the dielectric dummy fin.

### Claim 12 (depends on 11)

The device of claim 11, wherein a first top surface of the dielectric dummy fin is lower than a second top surface of the first protruding semiconductor fin.

### Claim 13 (depends on 12)

The device of claim 12, wherein the first top surface of the dielectric dummy fin is rounded.

### Claim 14 (depends on 11)

The device of claim 11, wherein first higher portions of the dielectric dummy fin have smaller widths than respective first lower portions of the dielectric dummy fin.

### Claim 15 (depends on 14)

The device of claim 14, wherein second higher portions of the dielectric dummy strip have greater widths than respective second lower portions of the dielectric dummy strip.

### Claim 16 (depends on 11)

The device of claim 11, wherein the second angle is an obtuse angle.

### Claim 17 (depends on 11)

The device of claim 11, wherein the first angle is an acute angle.

### Claim 18

A device comprising:
a shallow trench isolation region;
a dielectric dummy strip comprising a first sidewall contacting the shallow trench isolation region;
a dielectric dummy fin over and joined to the dielectric dummy strip, wherein first lower parts of the dielectric dummy fin are increasingly wider than respective first upper parts of the dielectric dummy fin;
a first protruding semiconductor fin and a second protruding semiconductor fin on opposing sides of the dielectric dummy fin; and
a gate stack on the first protruding semiconductor fin, wherein the gate stack contacts the dielectric dummy fin.

### Claim 19 (depends on 18)

The device of claim 18, wherein the dielectric dummy fin comprises a straight sidewall extending to the shallow trench isolation region.

### Claim 20 (depends on 18)

The device of claim 18, wherein upper parts of the dielectric dummy strip are increasingly wider than respective lower parts of the dielectric dummy strip.