# US 12,113,121 B2 · Uniform implant regions in a semiconductor ridge of a FinfET > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,121 B2 - Document ID: US12113121B2 - Status: Granted - Kind: B2 - Application number: 17/887,703 - Filed: 2022-08-15 - Published: 2022-12-08 - Granted: 2024-10-08 - Earliest claimed: 2020-10-16 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Ming-Yeh Chuang - Web page: https://patentgrep.com/patent/US12113121B2 ## CPC - H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants} - H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 84/834: {comprising FinFETs} - H10P 30/204: {into Group IV semiconductors} - H10P 30/212: {Through-implantation} - H10P 30/221: {characterised by the angle between the ion beam and the mask} - H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method for fabricating an integrated circuit is disclosed. The method comprises forming a semiconductor ridge over a semiconductor surface of a substrate and forming an implant screen on a top and sidewalls of the semiconductor ridge. The implant screen is at least two times thicker on the top of the semiconductor ridge relative to the sidewalls of the semiconductor ridge. The method further comprises implanting a dopant into the top and sidewalls of the semiconductor ridge. ## Claims ### Claim 1 An integrated circuit, comprising: a semiconductor fin located over a substrate, the fin having a top surface and side surfaces; and a doped region of the fin doped with phosphorous and arsenic, the top surface of the fin having a greater concentration of phosphorous than the side surfaces, and the side surfaces having a greater concentration of arsenic than the top surface. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the doped region is a drift region of a FinFET. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein a net concentration of phosphorous and arsenic varies by no more than ±50% between the top surface of the fin and the side surfaces of the fin. ### Claim 4 (depends on 1) The integrated circuit as recited in claim 1, further comprising a dielectric layer conformally covering the top surface and the side surfaces, the dielectric layer having a first thickness over the side surfaces and a greater second thickness over the top surface. ### Claim 5 (depends on 4) The integrated circuit as recited in claim 4, wherein the dielectric layer includes silicon oxide. ### Claim 6 (depends on 4) The integrated circuit as recited in claim 4, wherein the second thickness is at least about two times the first thickness. ### Claim 7 (depends on 4) The integrated circuit as recited in claim 4, wherein the first thickness is in a range from about 5 nm to about 15 nm, and the second thickness is in a range from about 30 nm to about 50 nm. ### Claim 8 (depends on 1) The integrated circuit as recited in claim 1, wherein the top surface of the fin and the side surfaces of the fin have about a same total dopant concentration. ### Claim 9 An integrated circuit (IC), comprising: a semiconductor fin located over a substrate; and a conformal dielectric layer over the fin, including sidewall portions over side surfaces of the fin and a top portion over a top surface of the fin, wherein the sidewall portions of the dielectric layer have a first thickness and the top portion of the dielectric layer has a second thickness at least about two times the first thickness. ### Claim 10 (depends on 9) The IC as recited in claim 9, wherein the first thickness is in a range from about 5 nm to about 15 nm, and the second thickness is in a range from about 30 nm to about 50 nm. ### Claim 11 (depends on 9) The IC as recited in claim 9, wherein the dielectric layer includes silicon oxide. ### Claim 12 (depends on 9) The IC as recited in claim 9, further comprising a doped region of the fin, the top surface of the fin having a first dopant concentration, and the side surfaces having a second dopant concentration about equal to the first dopant concentration. ### Claim 13 (depends on 9) The IC as recited in claim 9, wherein a net concentration of dopants having the same conductivity type varies by no more than ±50% between the top surface of the fin and the side surfaces of the fin. ### Claim 14 (depends on 9) The IC as recited in claim 9, further comprising a doped region of the fin including first and second dopants having a same conductivity type, the top surface of the fin having a greater concentration of the first dopant than the side surfaces, and the side surfaces having a greater concentration of the second dopant than the top surface. ### Claim 15 (depends on 14) The integrated circuit of claim 14, wherein the first dopant is boron and the second dopant is gallium. ### Claim 16 (depends on 14) The IC as recited in claim 14, wherein the first dopant is phosphorous and the second dopant is arsenic. ### Claim 17 (depends on 14) The IC as recited in claim 14, wherein the doped region is a drift region of a FinFET. ### Claim 18 An integrated circuit, comprising: a transistor having drift region including a semiconductor fin, the fin having a top surface, side surfaces, and a doped region, the doped region including first and second dopants having a same conductivity type, the top surface of the fin having a greater concentration of the first dopant than the side surfaces, and the side surfaces having a greater concentration of the second dopant than the top surface. ### Claim 19 An integrated circuit, comprising: a semiconductor fin located over a substrate, the fin having a top surface and side surfaces; and a doped region of the fin including first and second dopants having a same conductivity type, the top surface of the fin having a greater concentration of the first dopant than the side surfaces, and the side surfaces having a greater concentration of the second dopant than the top surface, wherein a net concentration of dopants having the same conductivity type varies by no more than ±50% between the top surface of the fin and the side surfaces of the fin. ### Claim 20 An integrated circuit, comprising: a semiconductor fin located over a substrate, the fin having a top surface and side surfaces; and a doped region of the fin including first and second dopants having a same conductivity type, the top surface of the fin having a greater concentration of the first dopant than the side surfaces, and the side surfaces having a greater concentration of the second dopant than the top surface, wherein the top surface of the fin and the side surfaces of the fin have about a same total dopant concentration.