# US 12,113,120 B2 · Gate electrode having a work-function layer including materials with different average grain sizes

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- Number: US 12,113,120 B2
- Document ID: US12113120B2
- Status: Granted
- Kind: B2
- Application number: 17/813,814
- Filed: 2022-07-20
- Published: 2022-11-10
- Granted: 2024-10-08
- Earliest claimed: 2019-11-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ru-Shang Hsiao; Ching-Hwanq Su; Pin Chia Su; Ying Hsin Lu; Ling-Sung Wang
- Web page: https://patentgrep.com/patent/US12113120B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

## Claims

### Claim 1

A device comprising:
a semiconductor region;
a gate dielectric over and contacting the semiconductor region;
a gate electrode over the gate dielectric, wherein the gate electrode comprises:
a metal-containing layer, wherein the metal-containing layer is a work-function layer, and the metal-containing layer comprises:
a lower layer having a first average grain size; and
an upper layer over the lower layer, wherein the lower layer and the upper layer comprise a same material, and the upper layer has a second average grain size greater than the first average grain size;
a glue layer over and contacting the work-function layer; and
a metal-filling region over the glue layer; and
source and drain regions on opposing sides of the gate electrode.

### Claim 2 (depends on 1)

The device of claim 1, wherein the metal-containing layer comprises a metal selected from the group consisting of tungsten, aluminum, cobalt, and combinations thereof.

### Claim 3 (depends on 1)

The device of claim 1, wherein the gate dielectric, the gate electrode, and the source and drain regions form parts of a p-type transistor, and the metal-containing layer has a work-function higher than about 4.5 eV.

### Claim 4 (depends on 1)

The device of claim 1 further comprising a gate contact plug over and contacting the upper layer of the gate electrode.

### Claim 5 (depends on 4)

The device of claim 4, wherein the gate contact plug further comprises a lower sub layer and an upper sub layer having different grain sizes.

### Claim 6 (depends on 5)

The device of claim 5, wherein the upper sub layer has a greater grain size than the lower sub layer.

### Claim 7 (depends on 1)

The device of claim 1, wherein the lower layer and the upper layer comprise a same metal.

### Claim 8 (depends on 1)

The device of claim 1, wherein a ratio of the second average grain size to the first average grain size is greater than about 100.

### Claim 9

A device comprising:
a semiconductor fin;
a gate dielectric on sidewalls and a top surface of the semiconductor fin;
a work-function layer over and contacting the gate dielectric, wherein the work-function layer has a U-shaped cross-sectional view shape, and wherein the work-function layer comprises a first bottom portion and first sidewall portions over and connecting to opposing ends of the first bottom portion, and wherein the work-function layer comprises:
a lower layer having a first average grain size; and
an upper layer over the lower layer, wherein the lower layer and the upper layer comprise a same material, and the upper layer has a second average grain size greater than the first average grain size;
a glue layer over the first bottom portion of the work-function layer, wherein the glue layer comprises a second bottom portion and second sidewall portions over and connecting to the second bottom portion; and
a metal layer having a polycrystalline structure over the second bottom portion of the glue layer.

### Claim 10 (depends on 9)

The device of claim 9, wherein a ratio of the second average grain size to the first average grain size is greater than about 100.

### Claim 11 (depends on 9)

The device of claim 9 further comprising a gate contact plug over and contacting the metal layer, wherein the gate contact plug comprises a lower portion and an upper portion over the lower portion, and the upper portion has a different average grain size than the lower portion.

### Claim 12 (depends on 11)

The device of claim 11, wherein the upper portion of the gate contact plug has a greater average grain size than the lower portion of the gate contact plug.

### Claim 13 (depends on 9)

The device of claim 9, wherein the metal layer comprises:
a first sub layer having a third average grain size; and
a second sub layer having a fourth average grain size different from the third average grain size.

### Claim 14 (depends on 13)

The device of claim 13, wherein the second sub layer is over the first sub layer, and the second average grain size is greater than the first average grain size.

### Claim 15 (depends on 13)

The device of claim 13, wherein the second sub layer is thicker than the first sub layer.

### Claim 16

A device comprising:
a semiconductor fin;
a gate dielectric on sidewalls and a top surface of the semiconductor fin;
a work-function layer over and contacting the gate dielectric, wherein the work-function layer has a polycrystalline structure, and the work-function layer comprises:
a first sub layer of the work-function layer; and
a second sub layer over the first sub layer, wherein the first sub layer and the second sub layer comprise same first elements, and the second sub layer has a different average grain size than the first sub layer; and
a metal layer over the work-function layer, wherein the metal layer comprises:
a third sub layer; and
a fourth sub layer, wherein the third sub layer and the fourth sub layer comprise same second elements, and wherein the fourth sub layer has a different average grain size than the third sub layer.

### Claim 17 (depends on 16)

The device of claim 16, wherein the gate dielectric, the work-function layer, and the metal layer are comprised in a transistor, and the device further comprises:
a guard ring encircling the transistor, wherein the guard ring comprises a plurality of dummy gate stacks, and wherein each of the dummy gate stacks comprises a stacked metal layer, with an upper part of the stacked metal layer having an average grain size greater than an average grain size of a corresponding lower part of the stacked metal layer.

### Claim 18 (depends on 17)

The device of claim 17, wherein the transistor is a p-type transistor.

### Claim 19 (depends on 16)

The device of claim 16, wherein the work-function layer comprises titanium nitride.

### Claim 20 (depends on 16)

The device of claim 16, wherein the metal layer comprises tungsten.