# US 12,113,119 B2 · Field effect transistor, preparation method thereof and integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,113,119 B2 - Document ID: US12113119B2 - Status: Granted - Kind: B2 - Application number: 17/573,852 - Filed: 2022-01-12 - Published: 2023-03-02 - Granted: 2024-10-08 - Earliest claimed: 2021-09-01 - Assignees: Hon Hai Precision Industry Co., Ltd. - Applicants: Hon Hai Precision Industry Co., Ltd. - Inventors: Chung-Yi Chen - Web page: https://patentgrep.com/patent/US12113119B2 ## CPC - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium} - H10D 30/017: {of FETs having two-dimensional material channels, e.g. TMD FETs} - H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 62/882: {Graphene} - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An FET, a method for manufacturing such FET, and an integrated circuit are disclosed. The FET includes a substrate carrying a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate. An insulating layer, an etching stop layer, and a protective layer are stacked sequentially on the channel layer. Source and drain electrodes are also formed. A material of the channel layer includes a 2D material. The FET defines two through holes extending through the insulating layer, the etching stop layer, and the protection layer and the channel layer is exposed, the two through holes carry the source and drain electrodes to form a top or direct contact with the channel layer. ## Claims ### Claim 1 A method for manufacturing a field effect transistor (FET), comprising: sequentially forming a gate electrode, a gate dielectric layer, and a channel layer on a substrate, wherein the gate electrode is closer to the substrate than the channel layer, and the channel layer is made of a two-dimensional (2D) material; sequentially forming an insulating layer, an etching stop layer and a protective layer on the channel layer, wherein the insulating layer is in direct contact with the channel layer and is electrically insulated; selectively etching the insulating layer, the etching stop layer, and the protective layer to form two through holes, the two through holes extending through the insulating layer, the etching stop layer, and the protective layer and exposing the channel layer; performing a plasma treatment on the channel layer; and forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively in a corresponding one of the two through holes and form a top contact with the channel layer. ### Claim 2 (depends on 1) The method for manufacturing an FET of claim 1, wherein selectively etching the insulating layer, the etching stop layer, and the protective layer comprises: patterning the protective layer by chemical etching to form two openings extending through the protective layer and exposing the etching stop layer; and patterning the etching stop layer and the protective layer by atomic layer etching to form the two through holes exposing the channel layer at the two openings. ### Claim 3 (depends on 1) The method for manufacturing an FET of claim 1, wherein the source electrode and the drain electrode are formed by atomic layer deposition. ### Claim 4 (depends on 1) The method for manufacturing an FET of claim 1, wherein the plasma treatment is O2 plasma treatment or N2 plasma treatment. ### Claim 5 (depends on 1) The method for manufacturing an FET of claim 1, wherein the 2D material is selected from a group consisting of graphene, black phosphorus, and 2D transition metal chalcogenides, a general formula of the 2D transition metal chalcogenides is MX2, M is one of molybdenum, tungsten, palladium, platinum, niobium, and tantalum, and X is one of sulfur, selenium, and tellurium. ### Claim 6 (depends on 1) The method for manufacturing an FET of claim 1, wherein a material of the insulating layer comprises boron nitride, a material of the etching stop layer comprises silicon nitride, and a material of the protective layer comprises silicon oxide. ### Claim 7 A field effect transistor (FET), comprising: a substrate; a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate, wherein the channel layer is made of a two-dimensional (2D) material, and the gate electrode is closer to the substrate than the channel layer; an insulating layer, an etching stop layer, and a protective layer sequentially stacked on the channel layer, wherein the insulating layer is in direct contact with the channel layer and is electrically insulated, and the FET defines two through holes extending through the insulating layer, the etching stop layer, and the protective layer and exposing the channel layer; and a source electrode and a drain electrode respectively in a corresponding one of the two through holes and forming a top contact with the channel layer. ### Claim 8 (depends on 7) The FET of claim 7, wherein the 2D material is selected from a group consisting of graphene, black phosphorus, and 2D transition metal chalcogenides, a general formula of the 2D transition metal chalcogenides is MX2, M is one of molybdenum, tungsten, palladium, platinum, niobium, and tantalum, and X is one of sulfur, selenium, and tellurium. ### Claim 9 (depends on 7) The FET of claim 7, wherein a material of the insulating layer comprises boron nitride, a material of the etching stop layer comprises silicon nitride, and a material of the protective layer comprises silicon oxide. ### Claim 10 (depends on 7) The FET of claim 7, wherein a material of the source electrode is selected from a group consisting of nickel, aluminum, platinum, copper, palladium, gold, titanium, and chromium; a material of the drain electrode is selected from a group consisting of nickel, aluminum, platinum, copper, palladium, gold, titanium, and chromium. ### Claim 11 (depends on 7) The FET of claim 7, wherein each of the source electrode and the drain electrode comprises a first metal layer in the corresponding one of the two through holes and forming the top contact with the channel layer, and a second metal layer on the first metal layer and partially covering a surface of the protection layer. ### Claim 12 (depends on 11) The FET of claim 11, wherein the channel layer is made of molybdenum disulfide, the first metal layer is made of nickel. ### Claim 13 (depends on 7) The FET of claim 7, wherein a material of the gate dielectric layer is selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride, and high-K materials. ### Claim 14 (depends on 13) The FET of claim 13, wherein high-K materials are selected from a group consisting of HfO2, HfSiO, HfSiON, HfLaO, HfTiO, HfZrO, Al2O3, La2O3, ZrO2 and LaAlO. ### Claim 15 An integrated circuit, comprising a peripheral circuit and at least one FET electrically connected to the peripheral circuit, the at least one FET comprising: a substrate; a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate, wherein the channel layer is made of a two-dimensional (2D) material, and the gate electrode is closer to the substrate than the channel layer; an insulating layer, an etching stop layer, and a protective layer sequentially stacked on the channel layer, wherein the insulating layer is electrically insulated and in direct contact with the channel layer, and the FET defines two through holes extending through the insulating layer, the etching stop layer, and the protective layer and exposing the channel layer; and a source electrode and a drain electrode respectively in a corresponding one of the two through holes and forming a top contact with the channel layer. ### Claim 16 (depends on 15) The integrated circuit of claim 15, wherein the 2D material is selected from a group consisting of graphene, black phosphorus, and 2D transition metal chalcogenides, a general formula of the 2D transition metal chalcogenides is MX2, M is one of molybdenum, tungsten, palladium, platinum, niobium, and tantalum, and X is one of sulfur, selenium, and tellurium. ### Claim 17 (depends on 15) The integrated circuit of claim 15, wherein a material of the insulating layer comprises boron nitride, a material of the etching stop layer comprises silicon nitride, and a material of the protective layer comprises silicon oxide. ### Claim 18 (depends on 15) The integrated circuit of claim 15, wherein a material of the source electrode is selected from a group consisting of nickel, aluminum, platinum, copper, palladium, gold, titanium, and chromium; a material of the drain electrode is selected from a group consisting of nickel, aluminum, platinum, copper, palladium, gold, titanium, and chromium. ### Claim 19 (depends on 15) The integrated circuit of claim 15, wherein each of the source electrode and the drain electrode comprises a first metal layer in the corresponding one of the two through holes and forming the top contact with the channel layer, and a second metal layer on the first metal layer and partially covering a surface of the protection layer; the channel layer is made of molybdenum disulfide, the first metal layer is made of nickel. ### Claim 20 (depends on 15) The integrated circuit of claim 15, wherein a material of the gate dielectric layer is selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride, and high-K materials.