# US 12,113,118 B2 · Stress-inducing silicon liner in semiconductor devices

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- Number: US 12,113,118 B2
- Document ID: US12113118B2
- Status: Granted
- Kind: B2
- Application number: 17/815,181
- Filed: 2022-07-26
- Published: 2022-11-17
- Granted: 2024-10-08
- Earliest claimed: 2019-09-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Bwo-Ning Chen; Xusheng Wu; Chang-Miao Liu; Shih-Hao Lin
- Web page: https://patentgrep.com/patent/US12113118B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3442: {N-type}
- H10P 14/3444: {P-type}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6309: {of silicon in uncombined form, i.e. pure silicon}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/6522: {introduced into a nitride material, e.g. changing SiN to SiON}
- H10P 14/6536: {by exposure to radiation, e.g. visible light}
- H10P 14/6687: {the compound comprising silicon and nitrogen}
- H10P 30/40: into insulating materials
- H10P 32/20: Diffusion for doping of insulating layers
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)}
- H10W 20/097: {by thermally treating}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.

## Claims

### Claim 1

A method, comprising:
providing a semiconductor device that includes a dummy gate structure disposed over a substrate and source/drain (S/D) features disposed adjacent to the dummy gate structure, wherein the dummy gate structure traverses a channel region between the S/D features;
forming a silicon liner over the semiconductor device, wherein the silicon liner includes elemental silicon;
forming an interlayer dielectric (ILD) layer over the silicon liner;
introducing a dopant species to the ILD layer;
after the introducing of the dopant species to the ILD layer, removing the dummy gate structure to form a gate trench;
after removing the dummy gate structure, performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner; and
forming a metal gate stack in the gate trench and over the oxidized silicon liner.

### Claim 2 (depends on 1)

The method of claim 1, wherein the thermal treatment is a first thermal treatment, the method further comprising performing a second thermal treatment to the ILD layer before introducing the dopant species, wherein performing the second thermal treatment partially oxidizes the silicon liner.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first thermal treatment is performed at a first temperature, and wherein the second thermal treatment is performed at a second temperature lower than the first temperature.

### Claim 4 (depends on 1)

The method of claim 1, wherein performing the thermal treatment oxidizes the elemental silicon in the silicon liner to form SixOy, and wherein a ratio of x to y is 1 or 1/2.

### Claim 5 (depends on 4)

The method of claim 4, wherein performing the thermal treatment fully oxidizes the silicon liner, such that the silicon liner is substantially free of elemental silicon.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the silicon liner includes conformally depositing the silicon liner over the semiconductor device,
wherein performing the thermal treatment to the doped ILD layer results in a fully oxidized silicon liner,
wherein a concentration of silicon dioxide in the fully oxidized silicon liner increases toward an interface between the doped ILD layer and the fully oxidized silicon liner.

### Claim 7 (depends on 1)

The method of claim 1, wherein oxidizing the silicon liner expands volume of the silicon liner, thereby exerting compressive stress on the channel region.

### Claim 8 (depends on 1)

The method of claim 1, wherein introducing the dopant species to the ILD layer includes performing an implantation process to the ILD layer, and wherein the dopant species includes nitrogen, silicon, germanium, or combinations thereof.

### Claim 9 (depends on 1)

The method of claim 1, wherein the semiconductor device is a first semiconductor device, wherein the S/D features are p-type S/D features, wherein the dummy gate structure is a first dummy gate structure, and wherein the channel region is a p-type channel region, the method further comprising:
providing a second semiconductor device disposed over the substrate, wherein the second semiconductor device includes n-type S/D features and a second dummy gate structure, such that the second dummy gate structure traverses an n-type channel region between the n-type S/D features, and wherein forming the silicon liner results in the silicon liner being formed over both of the first and the second semiconductor devices; and
before forming the ILD layer, selectively removing a portion of the silicon liner formed over the second semiconductor device, such that a remaining portion of the silicon liner is disposed over the first semiconductor device but not over the second semiconductor device.

### Claim 10

A method, comprising:
providing a semiconductor device that includes a dummy gate structure disposed over a substrate and source/drain (S/D) features disposed adjacent to the dummy gate structure, wherein the dummy gate structure traverses a channel region between the S/D features;
forming a silicon layer over the semiconductor device;
forming an interlayer dielectric (ILD) layer over the silicon layer, wherein the ILD layer includes excess oxygen;
annealing the ILD layer, thereby converting the silicon layer to a compound of silicon and oxidized silicon;
after annealing the ILD layer, introducing a dopant species to the ILD layer; and
after introducing the dopant species, performing a thermal treatment to the doped ILD layer, thereby converting the compound of silicon and oxidized silicon to a fully oxidized silicon layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
after introducing the dopant species and before performing the thermal treatment to the doped ILD layer, removing the dummy gate structure to form a gate trench, and
filling the gate trench with a metal gate stack.

### Claim 12 (depends on 10)

The method of claim 10, wherein the thermal treatment is performed at a first temperature, and wherein annealing the ILD layer is performed at a second temperature lower than the first temperature.

### Claim 13 (depends on 10)

The method of claim 10, further comprising, forming an etch-stop layer (ESL) over the semiconductor device and underlying the silicon layer, wherein the silicon layer is over a top surface of the ESL.

### Claim 14 (depends on 10)

The method of claim 10, wherein the fully oxidized silicon layer includes silicon oxide at a first concentration and silicon dioxide at a second concentration that is greater than the first concentration.

### Claim 15 (depends on 10)

The method of claim 10, wherein a concentration of silicon dioxide is greater in the ILD layer than in the fully oxidized silicon layer.

### Claim 16 (depends on 10)

The method of claim 10, wherein the channel region is a p-type channel region, and wherein annealing the ILD layer and performing the thermal treatment expand volume of the silicon layer, thereby exerting compressive stress on the p-type channel region.

### Claim 17

A method, comprising:
providing a semiconductor device that includes a dummy gate structure disposed over a substrate and source/drain (S/D) features disposed adjacent to the dummy gate structure, wherein the dummy gate structure traverses a channel region between the S/D features;
forming an etch-stop layer (ESL) over the semiconductor device, wherein the ESL is directly above the S/D features;
forming a silicon liner over a top surface of the ESL, wherein the silicon liner includes elemental silicon;
forming an interlayer dielectric (ILD) layer over the silicon liner;
introducing a dopant species to the ILD layer; and
performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner.

### Claim 18 (depends on 17)

The method of claim 17, wherein performing the thermal treatment oxidizes the elemental silicon in the silicon liner to form SixOy, and wherein a ratio of x to y is 1 or 1/2.

### Claim 19 (depends on 17)

The method of claim 17, before introducing the dopant species to the ILD layer, further comprising, annealing the ILD layer to oxidize a portion of the silicon liner to form a partially oxidized silicon liner at a temperature lower than a temperature of the thermal treatment,
wherein performing the thermal treatment to the doped ILD layer is after introducing the dopant species to the ILD layer.

### Claim 20 (depends on 17)

The method of claim 17, after introducing the dopant species and before performing the thermal treatment, further comprising, removing the dummy gate structure to form a gate trench.